8.3 Feature Description

8.3.1 Digital-to-Analog Converter (DAC) Architecture

Each output channel in the DACx3508 family of devices consists of string architecture with an output buffer

amplifier. Figure 8-1 shows a block diagram of the DAC architecture.

VOUTX

DAC

Buffer

Register

LDAC Trigger

(Synchronous Mode)

DAC

Active

Register

Serial Interface

DAC Data Register

WRITE

READ

(Asynchronous Mode)

BUF

AGND

VREFIN

VDD

String

Figure 8-1. DACx3508 DAC Architecture

8.3.1.1 DAC Transfer Function

The device writes the input data to the individual DAC Data registers in straight binary format. After a power-on

or a reset event, the device sets all DAC registers to zero-code. Equation 1 shows DAC transfer function.

(1)

where:

• N = resolution in bits: 10 (DAC53508) or 8 (DAC43508)

• DACn_DATA is the decimal equivalent of the binary code that is loaded to the DAC register

8.3.1.2 DAC Register Update and LDAC Functionality

The device stores the data written to the DAC Data registers in the DAC buffer registers. Transfer of data from

the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or

initiated by an LDAC trigger (synchronous mode). After the DAC active registers are updated, the DAC outputs

change to the new values.

The update mode for each DAC channel is determined by the status of LDAC pin.

In asynchronous mode (LDAC = low before the DAC write command), a write to the DAC data register results in

an immediate update of the DAC active register and DAC output at the end of SPI frame.

In synchronous mode (LDAC = high before the DAC write command), writing to the DAC data register does not

automatically update the DAC output. Instead, the update occurs only after LDAC is pulled low. The synchronous

update mode enables simultaneous update of all DAC outputs.

8.3.1.3 CLR Functionality

The CLR pin is an asynchronous input pin to the DAC. When this pin is pulled low, the DAC buffers and the DAC

active registers are set to zero code.

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DAC53508, DAC43508

SLASF08 – DECEMBER 2021

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