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DAC53508 Datasheet(PDF) 23 Page - Texas Instruments |
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DAC53508 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 38 page ![]() 8.6.1 DEVICE_CONFIG Register (address = 01h) [reset = 00FFh] Figure 8-3. DEVICE_CONFIG Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X RESERVED PDN-All PDNH PDNG PDNF PDNE PDND PDNC PDNB PDNA W-0h W-0h W-0b W-FFh Table 8-4. DEVICE_CONFIG Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 15-12 X W 0h Don't care 11-9 RESERVED W 00 Reserved 8 PDN-All W 0 Global power down bit: 0: Normal operation 1: All DAC channels and internal biasing blocks are powered down. 7-0 PDNx W FFh Channel-specific power down bits: 0: DACx powered up 1: DACx powered down with 10 kΩ pulldown resistor to AGND. 8.6.2 STATUS_TRIGGER Register (address = 02h) [reset = 0000h] Figure 8-4. STATUS_TRIGGER Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X SW_RST W-000h W-0h Table 8-5. STATUS_TRIGGER Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 15-4 X W 000h Don't care 3-0 SW_RST W 0h Device resets to default value when this bit field is set to 1010. Other values do not have any impact. 8.6.3 BRDCAST Register (address = 03h) [reset = 0000h] Figure 8-5. BRDCAST Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] X W-0h W-000h W-00b Table 8-6. BRDCAST Register Field Descriptions BIT FIELD TYPE RESET DESCRIPTION 15-12 X W 0h Don't care 11-2 BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] W 000h Writing to the BRDCAST register forces the DAC channel to update the active register data to BRDCAST_DATA. Data are MSB-aligned in straight-binary format and follow the format below: DAC53508: { DATA[9:0] } DAC43508: { DATA[7:0], x, x } x – Don’t care bits 1-0 X W 00 Don't care www.ti.com DAC53508, DAC43508 SLASF08 – DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DAC53508 DAC43508 |
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