DLPC4430 datasheet(20/49 Pages) TI

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TEST CONDITIONS

MIN

MAX

UNIT

tsu

Setup time, P2_A(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P2_A(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P2_B(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P2_B(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P2_C(9-0), valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P2_C(9-0), valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P2_VSYNC, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P2_VSYNC valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P2_HSYNC, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P2_HSYNC valid before P_CLK1↑↓, P_CLK2↑↓,

or P_CLK3↑↓

0.8

tsu

Setup time, P_DATAEN1, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P_DATAEN1 valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

tsu

Setup time, P_DATAEN2, valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

Hold time, P_DATAEN2 valid before P_CLK1↑↓,

P_CLK2↑↓, or P_CLK3↑↓

0.8

tw(A)

VSYNC Active Pulse Width

Video Line

tw(A)

HSYNC Active Pulse Width

Pixel

Clocks

(1)

ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are Asynchronous signals.

(2)

For frequencies (fclock) less than 175 MHZ, use following formula to obtain the jitter: Max Clock Jitter = +/- [ (1/ƒclock) – 5414 ps]

6.10 Port 3 Input Pixel Interface (via GPIO) Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fclock

Clock Frequency, P3_CLK

MHz

Cycle time, P3_CLK

18.5

37.1

tW(H)

Pulse Duration, high

50% to 50% reference points

(signal)

7.4

tW(L)

Pulse Duration, low

50% to 50% reference points

(signal)

7.4

tjp

Clock period jitter, P3_CLK

Max ƒclock

See (1)

Transition time, tt= tf/tr, P3_CLK

20% to 80% reference points

(signal)

1.0

5.0

Transition time, tt= tf/tr, P3_DATA(9-0)

20% to 80% reference points

(signal)

1.0

5.0

tsu

Setup time, P3_DATA(9-0) valid before P3_CLK↑↓

2.0

Hold time, P3_DATA(9-0) valid after P3_CLK↑↓

2.0

(1)

For frequencies less than 54 MHZ, use following formula to obtain the jitter: Jitter = [ (1/F) – 5414 ps].

DLPC4430

DLPS223 – DECEMBER 2021

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