EM65101AF datasheet(21/83 Pages) EMC

21 / 83 page

EM65101

128COM/160SEG 16 Gray Scale Level LCD Driver

Product Specification (V0.4) 08.15.2005

• 15

(This specification is subject to change without further notice)

SPOL = “0”

SPOL = “1”

Display RAM/Register

Display RAM Data

Control Register Data

Display RAM Data

After completing the 9-bit data transfer, or when making no access, be sure to set the

serial clock input (SCL) to “L.” Care should be taken during PCB layout to avoid

external noise from contaminating the SDA and SCL signals. To prevent any transfer

error due to external noise, release chip select (CSB = “H”) after every complete 9-bit

data transfer.

SDA

SCL

456

CSB

Figure 7-3 3-Wire Serial Interface

7.2 Writing Data to Display RAM and Control Register

The procedure to write data to the display RAM and Control Register is similar except

for the RS selection to select the accessed object.

RS = “L”: Display RAM data

RS = “H”: Control register data

In the case of the 80-family MPU, data is written at the rising edge of WRB. In the case

of the 68-family MPU, data is written at the falling edge of signal E.

7.2.1 Writing Data Operation

Data0

Data1

Data2

Data3

Data4

WRB

Write to control register

Write to display RAM

D7~D0

Data5

Figure 7-4 Writing Data Operation

EM65101AF Datasheet(PDF) 21 Page - ELAN Microelectronics Corp