LTC4155 datasheet(16/26 Pages) AD

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LTC4041

Rev A

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OPERATION

At the onset of backup mode, the supercapacitor charger

shuts off and the external NMOS pass transistors (MN1

and MN2 in the Block Diagram) are quickly turned off by

discharging the IGATE pin to ground, thereby disconnect-

ing the system output VSYS from the input and activat-

ing the backup boost converter to promptly deliver load

from the supercapacitor. Although the power-fail com-

parator has a hysteresis of approximately 40mV, it may

not be able to overcome the input voltage spike resulting

from the sudden collapse of the forward current from the

input to VSYS. To prevent repetitive mode switching, the

backup boost stays on for at least the minimum backup

time (tMIN-BACKUP) once activated. The minimum backup

time is programmed by connecting an external capacitor

between the CPF pin and ground. Refer to Programming

the Minimum Backup Time section in the Applications

Information. During this time, the power-fail comparator

output is ignored and an internal switch of approximately

270Ω pulls down the OVSNS pin to help discharge the

input. After the minimum backup time has elapsed, if the

power-fail comparator output indicates that power is still

not available, the backup boost continues to deliver the

load but the pull-down on the OVSNS pin is released.

When the power-fail comparator detects that input power

is available, the OVP charge pump starts to charge up

the IGATE pin but the backup boost converter continues

to deliver system load until IGATE is approximately 8V.

This ensures that the forward conduction path through

the external NMOS pass transistors has been established.

At this point, the backup boost gets deactivated and the

charger turns back on to charge the supercapacitor while

the system load gets delivered directly from the input to

VSYS through the pass transistors.

OPTIONAL INPUT OVERVOLTAGE PROTECTION (OVP)

The LTC4041 can protect itself from the inadvertent appli-

cation of excessive voltage with just two external com-

ponents: an N-channel FET (MN1) and a 6.2k resistor as

shown in the Block Diagram. The maximum safe overvolt-

age magnitude is determined by the choice of external

NMOS and its associated drain breakdown voltage.

The optional overvoltage protection (OVP) module con-

sists of two pins. The first, OVSNS, is used to measure the

applied voltage through an external resistor. The second,

IGATE, is an output used to drive the gate pins of two

external N-channel FETs, MN1 and MN2 (Block Diagram).

The voltage at the OVSNS pin will be lower than the OVP

input voltage by about 250mV due to the OVP circuit’s

quiescent current flowing through the OVSNS resistor.

When OVSNS is below 6V, an internal charge pump drives

IGATE to approximately 1.88 • VOVSNS. This enhances the

N-channel FETs providing a low impedance connection to

VSYS and power to the LTC4041. If OVSNS rises above 6V

due to a fault, IGATE is pulled down to ground, disabling

the external FETs to protect downstream circuitry. At the

same time, the backup boost converter activates to sup-

ply the system load from the supercapacitor. When the

voltage drops below 6V again, the external FETs are re-

enabled. If the OVP feature is not desired, remove MN1,

short OVSNS to VIN, and apply external power directly

to VIN.

SHUTDOWN MODE OPERATION

The LTC4041 can be shutdown almost entirely by pulling

both CHGEN and BSTEN pin above 1.2V. In this mode,

the internal charge pump is shutdown and IGATE is pulled

to ground disconnecting the forward path from input to

output via the external FETs. Only the internal OVP shunt

regulator remains active to monitor the input supply for

any possible overvoltage condition and consuming about

25μA via the OVSNS pin. Total current draw from the

SCAP pin drops to below 1μA (VSCAP = 2.5V) in shutdown.

Overtemperature (OT) Protection

When the LTC4041 die temperature exceeds 160°C (typi-

cal), the buck charger and backup boost are shut down

to prevent any thermal damage and remain in shutdown

until the die temperature falls to 145°C (typical). In OT,

the forward path from VIN to VSYS is disconnected by

pulling the gate voltage of the external FET(s) to ground.

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