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LTC4155 Datasheet(PDF) 22 Page - Analog Devices |
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LTC4155 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 26 page ![]() LTC4041 22 Rev A For more information www.analog.com APPLICATIONS INFORMATION 2. To minimize parasitic inductance, the ground plane should be as close as possible to the top plane of the PC board (Layer 2). High frequency currents in the hot loop tend to flow along a mirror path on the ground plane which is directly beneath the incident path on the top plane of the board as illustrated in Figure 4. If there are slits or cuts or drill-holes in this mirror path on the ground plane due to other traces, the current will be forced to go around the slits. When high frequency currents are not allowed to flow back through their natural least-area path, excessive volt- age will build up and radiated emissions will occur. So every effort should be made to keep the hot-loop current path as unbroken as possible. 3. The other important components that need to be placed close to the pins are the supercapacitor (con- nected to the SCAP pin) and the inductor L1. Even though the current through these components is continuous, they can change very abruptly due to a sudden change in load demand. Also, their traces should be wide enough to handle currents as high as the NMOS current limit (typical 6.5A) in backup boost mode. 4. Locate the VSYS dividers for BSTFB and RSTFB near the IC but away from the switching components. Kelvin the top of the resistor dividers to the positive terminal of CSYS. The bottom of the resistor dividers should return to the ground plane away from the hot- loop current path. The same is true for the PFI divider and the CAPFB divider. 5. The exposed pad on the backside of the LTC4041 package must be securely soldered to the PC board ground and also must have a group of vias con- necting it to the ground plane for optimum thermal performance. Also this is the only ground pin in the package, and it serves as the return path for both the control circuitry and the switching converter. 6. The IGATE pin for controlling the gates of the external pass transistors has extremely limited drive current. Care must be taken to minimize leakage to adjacent PC board traces. To minimize leakage, the trace can be guarded on the PC board by surrounding it with VSYS connected metal. Figure 4. High Frequency Ground Currents Follow Their Incident Path. Slices in the Ground Plane Cause High Voltage and Increased EMI 4041 F04 |
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