LT8331 datasheet(26/34 Pages) AD

26 / 34 page

LT8357

Rev. 0

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CDC has nearly a rectangular current waveform. During

the switch off-time, the current through CDC is IIN, while

approximately –IO flows during the on-time. The RMS

rating of the coupling capacitor is determined by the fol-

lowing equation:

IRMS(CDC) >IO(MAX)•

VOUT +VD

VIN(MIN)

A low ESR and ESL, X5R or X7R ceramic capacitor works

well for CDC.

Efficiency Considerations

The power efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Although all dissipative

elements in circuits produce losses, five main sources

account for most of the losses in LT8357 circuits:

1. DC I•VD loss. The largest power loss comes from the

forward voltage drop of the output diode and it causes

the efficiency drop at high output currents.

2. DC I2•R losses. These arise from the resistances of

the power MOSFET, sense resistor, inductor and PC

board traces and cause the efficiency to drop at high

output currents.

3. Transition loss. This loss arises from the brief amount

of time the power MOSFET spends in the saturated

region during switch node transition. It depends upon

the input voltage, load current, driver strength and

MOSFET capacitance, among other factors.

4. INTVCC current. This is the sum of the power MOSFET

gate driver and control circuit currents.

5. CIN and COUT loss. The input capacitor has the dif-

ficult job of filtering the large RMS input current in

the flyback converter. The output capacitor has the

difficult job of filtering the large RMS output current

in the boost, flyback and SEPIC converters. Both CIN

and COUT are required to have low ESR to minimize

APPLICATIONS INFORMATION

the AC I2•R loss and sufficient capacitance to prevent

the RMS current from causing additional upstream

losses in fuses or batteries.

When making adjustments to improve efficiency, the input

current is the best indicator of changes in efficiency. If you

make a change and the input current decreases, then the

efficiency has increased. If there is no change in the input

current, then there is no change in efficiency.

PC Board Layout Checklist

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board pro-

vides heat sinking for power components.

• The ground plane layer should not have any traces

and it should be as close as possible to the layer with

power MOSFET and output diode.

• Use immediate vias to connect the components to the

ground plane. Use several large vias for each power

component.

• Use planes for VIN and VOUT to maintain good voltage

filtering and to keep power losses low.

• Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of power components. Connect the copper areas to

any DC net (VIN or GND).

• Separate the signal and power grounds. All small-

signal components should return to the exposed GND

pad from the bottom, which is then tied to the power

GND close to the power components.

• Place the power MOSFET and output diode as close

to the controller as possible, keeping the power GND,

power MOSFET gate drive signals and switch node

traces short.

• Keep the high dV/dT switch nodes and power MOSFET

gate drive signals away from sensitive small-signal

nodes.

• Keep the following high dI/dT loops in different topol-

ogies as tight as possible with short leads and PCB

trace lengths to reduce inductive ringing:

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