| Electronic Components Datasheet Search |
|
AD7380 Datasheet(PDF) 5 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7380 Datasheet(HTML) 5 Page - Analog Devices |
|
5 / 31 page ![]() Data Sheet AD7381-4 Rev. 0 | Page 5 of 31 TIMING SPECIFICATIONS VCC = 3.0 V to3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V, TA = −40°C to +125°C, unless otherwise noted. For SCLK frequencies ≥ 70 MHz, load capacitance (CLOAD) = 10 pF. For SCLK frequencies < 70 MHz, CLOAD = 20 pF. When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed, such as ALERT. For full pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Table 4. Parameter Min Typ Max Unit Description tCYC 250 ns Time between conversions tSCLKED 5 ns CS falling edge to first SCLK falling edge tSCLK 12.5 ns SCLK period tSCLKH 5.5 ns SCLK high time tSCLKL 5.5 ns SCLK low time tCSH 20 ns CS pulse width tQUIET 20 ns Interface quiet time prior to conversion tSDOEN CS low to SDOA and SDOB enabled 5.5 ns VLOGIC ≥ 2.25V 8 ns 1.65V ≤ VLOGIC < 2.25 V tSDOH 2 SCLK rising edge to SDOA and SDOB hold time tSDOS SCLK rising edge to SDOA and SDOB setup time 5 ns VLOGIC ≥ 2.25 V 8 ns 1.65V ≤ VLOGIC < 2.25V tSDOT 8 ns CS rising edge to SDOA and SDOB high impedance tSDIS 4 ns SDI setup time prior to SCLK falling edge tSDIH 4 ns SDI hold time after SCLK falling edge tSCLKCS 0 ns SCLK rising edge to CS rising edge tCONVERT 190 ns Conversion time tACQUIRE 110 ns Acquire time tRESET Valid time to start conversion after software reset (see Figure 35) 250 ns Valid time to start conversion after soft reset 800 ns Valid time to start conversion after hard reset tPOWERUP Supply active to conversion 5 ms First conversion allowed 11 ms Settled to within 1% with internal reference 5 ms Settled to within 1% with external reference tREGWRITE 5 ms Supply active to register read write access allowed tSTARTUP Exiting shutdown mode to conversion 11 ms Settled to within 1% with internal reference 10 µs Settled to within 1% with external reference tCONVERT0 6 8 10 ns Conversion time for first sample in oversampling (OS) normal mode tCONVERTx tCONVERT0 + (250 × (x – 1)) ns Conversion time for xth sample in OS normal mode tALERTS 220 ns Time from CS to ALERT indication tALERTC 10 ns Time from CS to ALERT clear tALERTS_NOS 20 ns Time from internal conversion with exceeded threshold to ALERT indication |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |