AD7381-4

Data Sheet

Rev. 0 | Page 30 of 31

ALERT LOW THRESHOLD REGISTER

Addressing

Alert Low

0

0

1

0

2

0

3

0

4

0

5

0

6

0

7

0

8

0

9

0

10

0

11

1

12

0

13

0

14

0

15

0

[15:12] ADDRESSING (R/W)

[11:0] ALERT_LOW (R/W)

Table 21. Bit Descriptions for Alert Low Threshold Register

Bits

Bit Name

Description

Reset

Access

[15:12]

ADDRESSING

Addressing. Bits[15:12] define the address of the relevant register. See the Addressing

Registers section for further details.

0x0

R/W

[11:0]

ALERT_LOW

Alert Low. Bits[11:0] from ALERT_LOW move to the MSBs of the internal alert low register,

D[15:4]. The remaining bits, D[3:0] of the internal register are fixed at 0x0. Sets an alert when

the converter result is below the value in the alert low threshold register, and the alert is

disabled when it is above the value in the alert low threshold register.

0x800

R/W

ALERT HIGH THRESHOLD REGISTER

Addressing

Alert High

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

1

10

1

11

0

12

0

13

0

14

0

15

0

[15:12] ADDRESSING (R/W)

[11:0] ALERT_HIGH (R/W)

Table 22. Bit Descriptions for Alert High Threshold Register

Bits

Bit Name

Description

Reset

Access

[15:12]

ADDRESSING

Addressing. Bits[15:12] define the address of the relevant register. See the Addressing

Registers section for further details.

0x0

R/W

[11:0]

ALERT_HIGH

Alert High. Bits D[11:0] from ALERT_HIGH move to the MSBs of the internal alert high

register, D[15:4]. The remaining bits, D[3:0] of the internal are fixed at 0xF. Sets an alert when

the converter result is above the value in the alert high threshold register, and the alert is

disabled when it is below the value in the alert high threshold register.

0x7FF

R/W