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AD7381-4

Data Sheet

Rev. 0 | Page 14 of 31

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7381-4 is a high speed, quad, fully differential, 14-bit, SAR

ADC. The device operates from a 3.0 V to 3.6 V power supply

and features throughput rates up to 4 MSPS.

The AD7381-4 contains four successive approximation ADCs,

and a serial interface with four separate data output pins. The

device is housed in a 24-lead LFCSP, offering the user

considerable space-saving advantages over alternative

solutions.

Data is accessed from the device via the serial interface. The

interface can be operated with two, four, or one serial output.

The AD7381-4 has an on-chip 2.5 V internal reference

(10 ppm/°C). If an external reference is desired, the internal

reference can be disabled, and an external reference voltage

ranging from 2.5 V to 3.3 V can be supplied. If the internal

reference is used elsewhere in the system, the reference output

must be buffered. The differential analog input range for the

AD7381-4 is VCM ± VREF/2.

The AD7381-4 features on-chip oversampling blocks to

improve performance. Normal averaging and rolling average

oversampling modes are available. Power-down options to

allow power saving between conversions are available.

Configuration of the device is implemented via the standard

serial interface, as described in the Interface section.

CONVERTER OPERATION

The AD7381-4 has four successive approximation ADCs, each

based around two capacitive DACs. Figure 27 and Figure 28

show simplified schematics of one of these ADCs in acquisition

and conversion phases, respectively. The ADC comprises

control logic, a SAR, and two capacitive DACs. In Figure 27

(the acquisition phase), SW3 is closed, SW1 and SW2 are in

Position A, the comparator is held in a balanced condition,

and the sampling capacitor (CS) arrays can acquire the

differential signal on the input.

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

AINx+

VREF

AINx–

Figure 27. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 28), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected when the

conversion begins. The control logic and charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator back

into a balanced condition. When the comparator is rebalanced,

the conversion is complete. The control logic generates the

ADC output code. The output impedances of the sources

driving the AINx+ and AINx− pins must be matched. Otherwise,

the two inputs have different settling times, resulting in errors.

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

AINx+

VREF

AINx–

Figure 28. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 29 shows the equivalent circuit of the analog input struc-

ture of the AD7381-4. The four diodes provide ESD protection

for the analog inputs. Ensure that the analog input signals never

exceed the supply rails by more than 300 mV. Exceeding the limit

causes these diodes to become forward-biased and start

conducting into the substrate. These diodes can conduct up to

10 mA without causing irreversible damage to the device.

The C1 capacitors in Figure 29 are typically 3 pF and can

primarily be attributed to pin capacitance. The R1 resistors

are lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 200 Ω.

The C2 capacitors are the ADC sampling capacitors with a

typical capacitance of 15 pF.

AINx+

AINx–

Figure 29. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

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