MAX11901 datasheet(20/29 Pages) MAXIM

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In the split reading mode, the data is read during the track

phase and the following SAR conversion phase. Figure 7

shows the descriptive timing diagram.

At higher sampling rates, the track time may not be long

enough to allow reading all 16 bits of data. In this case,

the data read can be started in track mode, and then

continued in the subsequent SAR conversion phase. Note

that the read operation must be completed before DOUT

goes low, signaling the end of the SAR conversion phase.

Also note that no SCLK pulses should be applied close to

the sampling edge (rising edge of CNVST), to safeguard

the sampling edge from digital noise (see the Quiet Time

specification t10). This split reading feature can be used

to accommodate slower SPI clocks.

SPI Timing Diagram

Figure 8 shows the typical digital SPI interface connection

between the MAX11901 and host processor.

The dashed connections are optional.

Figure 9 shows the timing diagram for configuration reg-

isters.

Figure 10 shows the timing diagram for data output read-

ing after conversion.

Figure 7. Split Read Mode

Figure 8. SPI Interface Connection

CNVST

SCLK

DOUT

Track

Read Data

Sample 1

SAR Conversion

1/Sample Rate

Sample 2

MSB MSB-1

LSB+1 LSB

MSB MSB-1

Track

Read Data

SAR Conversion

1/Sample Rate

Quiet Time

Reading sample 1

Sample 1

Sample 2

Host Processor

CNVST

DOUT

SCLK

DIN

MAX11901

CNVST

SCLK

DOUT

DIN

IRQ

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Maxim Integrated │ 20

MAX11901

16-Bit, 1.6Msps, Low-Power,

Fully Differential SAR ADC

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