ADXL367 datasheet(42/64 Pages) AD

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Data Sheet

ADXL367

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Rev. 0 | 42 of 64

Table 46. Bit Descriptions for FIFO_CONTROL

Bits

Bit Name

Description

Reset

Access

11: in triggered mode, the FIFO saves samples surrounding an activity event. The operation is similar to

a one time run trigger on an oscilloscope. The number of samples to be saved prior to the activity event

is specified in FIFO_SAMPLES register, along with the FIFO_SAMPLES[8] bit in this FIFO_CONTROL

stored, and the FIFO_WATER_MARK interrupt is activated (if mapped to an interrupt pin), a FIFO read

must be taken before another interrupt can be activated.

FIFO SAMPLE REGISTER

Address: 0x29, Reset: 0x80, Name: FIFO_SAMPLES

Table 47. Bit Descriptions for FIFO_SAMPLES

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

FIFO_SAMPLES[7:0]

The value in this register specifies the number of samples sets to store in the FIFO. If the

x-axis, y-axis, and z-axis are configured to be stored in the FIFO and a value of 2 is written to

the FIFO samples, then 6 samples are written into the FIFO. The full range of FIFO samples

is 0 to 511. The default value of this register is 0x80 to avoid triggering the FIFO watermark

interrupt.

0x80

R/W

INTERRUPT PIN 1 ENABLES (LOWER) REGISTER

Address: 0x2A, Reset: 0x00, Name: INTMAP1_LOWER

Table 48. Bit Descriptions for INTMAP1_LOWER

Bits

Bit Name

Description

Reset

Access

INT_LOW_INT1

Configures whether the pin operates in active high (Bit 7 low) or active low (Bit 7 high) mode.

0x0

R/W

1: interrupt enabled.

0: interrupt disabled.

AWAKE_INT1

1 = maps the awake status to the INT1 pin.

0x0

R/W

1: interrupt enabled.

0: interrupt disabled.

INACT_INT1

1 = maps the inactivity status to the INT1 pin.

0x0

R/W

1: interrupt enabled.

0: interrupt disabled.

ACT_INT1

Enable the activity detected interrupt to the INT1 pin.

0x0

R/W

1: interrupt enabled.

0: interrupt disabled.

FIFO_OVERRUN_INT1

1 = maps the FIFO overrun status to the INT1 pin.

0x0

R/W

1: interrupt enabled.

0: interrupt disabled.

FIFO_WATERMARK_INT1

1 = maps the FIFO watermark status to the INT1 pin.

0x0

R/W

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