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AFE7903 Datasheet(PDF) 3 Page - Texas Instruments |
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AFE7903 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 152 page ![]() 4 Description (continued) Each receiver chain includes a 25 dB range DSA (Digital Step Attenuator), followed by a 3 GSPS ADC (analog- to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 400 MHz for two RX. The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock. 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2022 * Initial Release www.ti.com AFE7903 SBASAK2 – MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: AFE7903 |
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