AD9371BBCZ datasheet(11/57 Pages) AD

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Data Sheet

AD9371

Rev. B | Page 11 of 57

JESD204B DATA OUTPUT TIMING

Unit Interval

162.76

1627.6

Data Rate per Channel (Nonreturn to Zero (NRZ))

614.4

6144

Mbps

Rise Time

20% to 80% in 100 Ω load

Fall Time

20% to 80% in 100 Ω load

Output Common-Mode Voltage

VCM

1.8

AC-coupled

Termination Voltage (VTT) = 1.2 V

735

1135

DC-coupled

Differential Output Voltage

VDIFF

360

466

770

Short-Circuit Current

IDSHORT

−100

+100

Differential Termination Impedance

ZRDIFF

100

120

Total Jitter

48.8

Bit error rate (BER) = 10−15

Uncorrelated Bounded High Probability Jitter

UBHPJ

1.2

24.4

Duty-Cycle Distortion

DCD

8.1

SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal

2.5

See Figure 2 and Figure 3

SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal

−1.5

See Figure 2 and Figure 3

JESD204B DATA INPUT TIMING

Unit Interval

162.76

1627.6

Data Rate per Channel (NRZ)

614.4

6144

Mbps

Input Common-Mode Voltage

VCM

0.05

1.85

AC-coupled

VTT = 1.2 V

720

1200

DC-coupled

Differential Input Voltage

VDIFF

125

750

VTT Source Impedance

ZTT

1.2

Differential Termination Impedance

ZRDIFF

106

120

VTT

AC-Coupled

1.27

1.33

DC-Coupled

1.14

1.26

Timing Diagrams

AT DEVICE PINS

DEV_CLK_IN

tH = –1.5ns

tS = +2.5ns

t'H = +0.5ns

t'S = +0.5ns

AT DIGITAL CORE

t'H

t'S

t'H

DEV_CLK_IN DELAY

IN REFERENCE TO SYSREF

CLK DELAY = 2ns

Figure 2. SYSREF_IN Signal Setup and Hold Timing

DEV_CLK_IN

SYSREF_IN

VALID SYSREF_IN

tH = –1.5ns

tS = +2.5ns

INVALID SYSREF_IN

Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal

AD9371BBCZ Datasheet(PDF) 11 Page - Analog Devices

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