SIC401DB datasheet(18/30 Pages) VISHAY

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SiC401A, SiC401BCD

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Vishay Siliconix

S20-0483-Rev. E, 29-Jun-2020

Document Number: 63835

For technical questions, contact: powerictechsupport@vishay.com

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Fig. 9 - Soft-Start Timing Diagram

Pre-Bias Start-Up

The SiC401A/B can start up normally even when there is an

existing output voltage present. The soft start time is still the

same as normal start up (when the output voltage starts

from zero). The output voltage starts to ramp up when 40 %

of the voltage at SS pin meets the existing FB voltage level.

Pre-bias startup is achieved by turning off the lower gate

when the inductor current falls below zero. This method

prevents the output voltage from discharging.

Power Good Output

The PGOOD (power good) output is an open-drain output

which requires a pull-up resistor. When the voltage at the FB

pin is 10 % below the nominal voltage, PGOOD is pulled low.

It is held low until the output voltage returns above -8 % of

nominal.

PGOOD will transition low if the VFB pin exceeds +20 % of

nominal, which is also the over voltage shutdown threshold.

PGOOD also pulls low if the EN/PSV pin is low when VDD is

present.

Output Over Voltage Protection

Over voltage protection becomes active as soon as the

device is enabled. The threshold is set at 600 mV +20 %

(720 mV). When VFB exceeds the OVP threshold, DL latches

high and the low side MOSFET is turned on. DL remains high

and the controller remains off, until the EN/PSV input is

toggled or VDD is cycled. There is a 5 μs delay built into the

OVP detector to prevent false transitions. PGOOD is also low

after an OVP event.

Output Under Voltage Protection

When VFB falls 25 % below its nominal voltage (falls to

450 mV) for eight consecutive clock cycles, the switcher is

shut off and the DH and DL drives are pulled low to tristate

the MOSFETs. The controller stays off until EN/PSV is

toggled or VDD is cycled.



VDD UVLO, and POR

UVLO (Under Voltage Lock-Out) circuitry inhibits switching

and tri-states the DH/DL drivers until VDD rises above 3 V. An

internal POR (Power-On Reset) occurs when VDD exceeds

3 V, which resets the fault latch and a soft-start counter

cycle begins which prepares for soft-start. The SiC401A/B

then begins a soft-start cycle. The PWM will shut off if VDD

falls below 2.4 V.

LDO Regulator

SiC401A/B has an option to bias the switcher by using an

internal LDO from VIN. The LDO output is connected to VDD

internally. The output of the LDO is programmable by using

external resistors from the VDD pin to AGND (see Fig. 10). The

feedback pin (FBL) for the LDO is regulated to 750 mV.

Fig. 10 - LDO Output Voltage Selection

The LDO output voltage is set by the following equation.



A minimum capacitance of 1 μF referenced to AGND is

normally required at the output of the LDO for stability.

Note that if the LDO voltage is set lower than 4.5 V, the

minimum output capacitance for the LDO is 10 μF.

LDO ENL Functions

The ENL input is used to enable/disable the internal LDO.

When ENL is a logic low, the LDO is off. When ENL is above

the VIN UVLO threshold, the LDO is enabled and the

switcher is also enabled if the EN/PSV and VDD are above

their threshold. The table below summarizes the function of

ENL and EN/PSV pins.



The ENL pin also acts as the switcher under voltage lockout

for the VIN supply. When SiC401A/B is self-biased from the

LDO and runs from the VIN power source only, the VIN UVLO

feature can be used to prevent false UV faults for the PWM

output by programming with a resistor divider at the VIN,

ENL and AGND pins. When SiC401A/B has an external bias

voltage at VDD and the ENL pin is used to program the VIN

EN/PSV

ENL

LDO

SWITCHER

Disabled

Low, < 0.4 V

Off

Enabled

Low, < 0.4 V

Off

Disabled

1 V < High < 2.6 V

Off

Enabled

1 V < High < 2.6 V

Off

Disabled

High, > 2.6 V

Off

Enabled

High, > 2.6 V

LDO = 750 mV x

1 +

LDO1

LDO2

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