SIC401DB datasheet(23/30 Pages) VISHAY

23 / 30 page

SiC401A, SiC401BCD

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Vishay Siliconix

S20-0483-Rev. E, 29-Jun-2020

Document Number: 63835

For technical questions, contact: powerictechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

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Select CL (typical 10 nF) and RL to match with L and DCR

time constant using the following equation.

Select CC by using the following equation.

The resistor values (R1 and R2) in the voltage divider circuit

set the VOUT for the switcher. The typical value for CC is from

10 pF to 1 nF.

Dropout Performance

The output voltage adjustment range for continuous

conduction operation is limited by the fixed 250 ns (typical)

minimum off-time of the one-shot. When working with low

input voltages, the duty-factor limit must be calculated using

worst-case values for on and off times.

The duty-factor limitation is shown by the next equation.

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy (VOUT Controller)

Three factors affect VOUT accuracy: the trip point of the

FB error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator offset is trimmed so that under static conditions

it trips when the feedback pin is 600 mV, 1 %.

The on-time pulse from the SiC401A/B in the design

example is calculated to give a pseudo-fixed frequency of

300 kHz. Some frequency variation with line and load is

expected. This variation changes the output ripple voltage.

Because adaptive on-time converters regulate to the valley

of the output ripple, ½ of the output ripple appears as a DC

regulation error. For example, if the output ripple is 50 mV

with VIN = 6 V, then the measured DC output will be 25 mV

above the comparator trip point.

If the ripple increases to 80 mV with VIN = 17 V, then the

measured DC output will be 40 mV above the comparator

trip. The best way to minimize this effect is to minimize the

output ripple.

The use of 1 % feedback resistors may result in up to 1 %

error. If tighter DC accuracy is required, 0.1 % resistors

should be used.

The output inductor value may change with current. This will

change the output ripple and therefore will have a minor

effect on the DC output voltage. The output ESR also affects

the output ripple and thus has a minor effect on the DC

output voltage.

Switching Frequency Variation

The switching frequency varies with load current as a result

of the power losses in the MOSFETs and DCR of the

inductor. For a conventional PWM constant-frequency

converter, as load increases the duty cycle also increases

slightly to compensate for IR and switching losses in the

MOSFETs and inductor. An adaptive on-time converter

must also compensate for the same losses by increasing the

effective duty cycle (more time is spent drawing energy from

VIN as losses increase). The on-time is essentially constant

for a given VOUT/VIN combination, to offset the losses the

off-time will tend to reduce slightly as load increases. The

net effect is that switching frequency increases slightly with

increasing load.

HIGH OUTPUT VOLTAGE OPERATION

For the SiC40X family the recommended maximum output

voltage of no more than 75 % of VIN.

For applications where an output voltage greater than 5 V is

required a resistive network should be used to step down the

output voltage in order to provide the VOUT_PIN with 4.5 V.

For example, if an output voltage of VOUT = 8.5 V is required,

setting R2 = 10 k and VOUT_PIN = 4.5 V results in R1 = 8870 

The switching frequency will also need recalculating using a

VOUT_PIN magnitude of 4.5 V.

Fig. 18 - Resistor Divider Network allows 4.5 V at the VOUT Pin

RL =

DCR x CL

CC ≈

R1//R2

2 x

π x fSW

DUTY =

tON(min.)

tON(min.) x tOFF(max.)

1 =

2 (VOUT - VOUT_PIN)

OUT_PIN

sw =

OUT_PIN

ON x VIN

SiC40X

Cout

Vout

VOUT_PIN

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