PCM1820 datasheet(7/41 Pages) TI

7 / 41 page

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,

TDM slave mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIL

Low-level digital input logic

voltage threshold

All digital pins except FMT0, IOVDD 1.8-V operation

–0.3

0.30 ×

IOVDD

All digital pins except FMT0, IOVDD 3.3-V operation

–0.3

0.8

FMT0 Pin

–0.3

0.8

VIH

High-level digital input logic

voltage threshold

All digital pins except FMT0, IOVDD 1.8-V operation

0.7 × IOVDD

IOVDD + 0.3

All digital pins except FMT0, IOVDD 3.3-V operation

2.1

IOVDD + 0.3

FMT0 Pin

2.1

AVDD + 0.3

VOL

Low-level digital output

voltage

All digital pins, IOL = –2 mA, IOVDD 1.8-V operation

0.45

All digital pins, IOL = –2 mA, IOVDD 3.3-V operation

0.4

VOH

High-level digital output

voltage

All digital pins, IOH = 2 mA, IOVDD 1.8-V operation

IOVDD –

0.45

All digital pins, IOH = 2 mA, IOVDD 3.3-V operation

2.4

IIH

Input logic-high leakage for

digital inputs

All digital pins, input = IOVDD

–5

0.1

µA

IIL

Input logic-low leakage for

digital inputs

All digital pins, input = 0 V

–5

0.1

µA

CIN

Input capacitance for digital

inputs

All digital pins

RPD

Pulldown resistance for

digital I/O pins when

asserted on

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

IAVDD

Current consumption with

all Clocks disabled

AVDD = 3.3 V, internal AREG

0.5

IIOVDD

All external clocks stopped, IOVDD = 3.3 V

0.5

µA

IIOVDD

All external clocks stopped, IOVDD = 1.8 V

0.3

IAVDD

Current consumption with

ADC 2-channel operating

at fS 16-kHz, BCLK = 256

× fS and DRE disabled

AVDD = 3.3 V, internal AREG

11.9

IIOVDD

IOVDD = 3.3 V

0.05

IIOVDD

IOVDD = 1.8 V

0.02

IAVDD

Current consumption with

ADC 2-channel operating

at fS 48-kHz, BCLK = 256

× fS and DRE disabled

AVDD = 3.3 V, internal AREG

12.9

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

IAVDD

Current consumption with

ADC 2-channel operating

at fS 48-kHz, BCLK = 256

× fS and DRE enabled

AVDD = 3.3 V, internal AREG

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

(1)

Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured

A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.

(2)

All performance measurements done with a 20-kHz, low-pass filter and, where noted, an A-weighted filter. Failure to use such a filter

may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter

removes out-of-band noise, which, although not audible, may affect dynamic specification values.

(3)

For best distortion performance, use input AC-coupling capacitors with a low-voltage-coefficient.

(4)

Gain drift =gain_variation(in temperature range)/ typical gain value(gain at room temperature) / temperature range × 106 measured

with gain in linear scale.

(5)

Phase drift =phase_deviation(in temperature range)/ (temperature range).

7.6 Timing Requirements: TDM or I2S Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted)

MIN

NOM

MAX

UNIT

t(BCLK)

BCLK period

tH(BCLK)

BCLK high pulse duration (1)

tL(BCLK)

BCLK low pulse duration (1)

tSU(FSYNC)

FSYNC setup time

tHLD(FSYNC)

FSYNC hold time

tr(BCLK)

BCLK rise time

10% - 90% rise time(2)

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PCM1822

SBASAK0 – DECEMBER 2020 – REVISED MAY 2022

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