equal to the number of active output channels (including left and right slots) times the 32-bits word length of the

output channel data. The device FSYNC low pulse must be a number of BCLK cycles wide that is greater than

or equal to the number of active left slots times the 32-bits data word length. Similarly, the FSYNC high pulse

must be a number of BCLK cycles wide that is greater than or equal to the number of active right slots times the

32-bits data word length. The device transmit zero data value on SDOUT for the extra unused bit clock cycles.

8.3.3 Phase-Locked Loop (PLL) and Clock Generation

The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the

ADC modulator and digital filter engine, as well as other control blocks.

In slave mode of operation, the device supports the various output data sample rates (of the FSYNC signal

frequency) and the BCLK to FSYNC ratio to configure all clock dividers, including the PLL configuration,

internally without host programming. Table 8-3 and Table 8-4 list the supported FSYNC and BCLK frequencies.

Table 8-3. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies

BCLK TO

FSYNC RATIO

BCLK (MHz)

FSYNC

(8 kHz)

FSYNC

(16 kHz)

FSYNC

(24 kHz)

FSYNC

(32 kHz)

FSYNC

(48 kHz)

FSYNC

(96 kHz)

FSYNC

(192 kHz)

16

Reserved

0.256

0.384

0.512

0.768

1.536

3.072

24

Reserved

0.384

0.576

0.768

1.152

2.304

4.608

32

0.256

0.512

0.768

1.024

1.536

3.072

6.144

48

0.384

0.768

1.152

1.536

2.304

4.608

9.216

64

0.512

1.024

1.536

2.048

3.072

6.144

12.288

96

0.768

1.536

2.304

3.072

4.608

9.216

18.432

128

1.024

2.048

3.072

4.096

6.144

12.288

24.576

192

1.536

3.072

4.608

6.144

9.216

18.432

Reserved

256

2.048

4.096

6.144

8.192

12.288

24.576

Reserved

384

3.072

6.144

9.216

12.288

18.432

Reserved

Reserved

512

4.096

8.192

12.288

16.384

24.576

Reserved

Reserved

Table 8-4. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies

BCLK TO

FSYNC RATIO

BCLK (MHz)

FSYNC

(7.35 kHz)

FSYNC

(14.7 kHz)

FSYNC

(22.05 kHz)

FSYNC

(29.4 kHz)

FSYNC

(44.1 kHz)

FSYNC

(88.2 kHz)

FSYNC

(176.4 kHz)

16

Reserved

Reserved

0.3528

0.4704

0.7056

1.4112

2.8224

24

Reserved

0.3528

0.5292

0.7056

1.0584

2.1168

4.2336

32

Reserved

0.4704

0.7056

0.9408

1.4112

2.8224

5.6448

48

0.3528

0.7056

1.0584

1.4112

2.1168

4.2336

8.4672

64

0.4704

0.9408

1.4112

1.8816

2.8224

5.6448

11.2896

96

0.7056

1.4112

2.1168

2.8224

4.2336

8.4672

16.9344

128

0.9408

1.8816

2.8224

3.7632

5.6448

11.2896

22.5792

192

1.4112

2.8224

4.2336

5.6448

8.4672

16.9344

Reserved

256

1.8816

3.7632

5.6448

7.5264

11.2896

22.5792

Reserved

384

2.8224

5.6448

8.4672

11.2896

16.9344

Reserved

Reserved

512

3.7632

7.5264

11.2896

15.0528

22.5792

Reserved

Reserved

In the master mode of operation, the device uses the MD1 pin (as the system clock, MCLK) as the reference

selection for the master mode using the MD0 pin.

PCM1822

SBASAK0 – DECEMBER 2020 – REVISED MAY 2022

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