Table 8-5. System Clock Selection for the Master Mode

MD0

SYSTEM CLOCK SELECTION (Valid for Master Mode Only)

LOW

HIGH

See Table 8-7 and Table 8-20 for the MD0 and MD1 pin function in the slave mode of operation.

8.3.4 Input Channel Configurations

The device consists of two pairs of analog input pins (INxP and INxM) as differential inputs for the recording

channel. The device supports simultaneous recording of up to two channels using the high-performance stereo

ADC. The input source for the analog pins can be from electret condenser analog microphones, micro electrical-

mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board.

The voice or audio signal inputs must be capacitively coupled (AC-coupled) to the device and, for best distortion

performance, use the low-voltage coefficient capacitors for AC coupling. The typical input impedance for the

PCM1822 is 2.5 kΩ for the INxP or INxM pins. The value of the coupling capacitor in AC-coupled mode

must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not

affect the signal content. Before proper recording can begin, this coupling capacitor must be charged up to the

common-mode voltage at power-up. To enable quick charging, the device has a quick charge scheme to speed

up the charging of the coupling capacitor at power-up. The default value of the quick-charge timing is set for a

coupling capacitor up to 1 µF.

8.3.5 Reference Voltage

All audio data converters require a DC reference voltage. The PCM1822 achieves low-noise performance by

internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap

circuit with high PSRR performance. This audio converter reference voltage must be filtered externally using a

minimum 1-µF capacitor connected from the VREF pin to analog ground (AVSS). The value of this reference

required minimum AVDD voltage for this VREF voltage is 3 V. Do not connect any external load to a VREF pin.

8.3.6 Signal-Chain Processing

The PCM1822 signal chain is comprised of very-low-noise, high-performance, and low-power analog blocks and

highly flexible and programmable digital processing blocks. The high performance and flexibility combined with a

compact package makes the PCM1822 optimized for a variety of end-equipments and applications that require

multichannel audio capture. Figure 8-7 shows a conceptual block diagram for the PCM1822 that highlights the

various building blocks used in the signal chain, and how the blocks interact in the signal chain. The PCM1822

does not support DRE.

DRE

Amplifier

ADC

Configurable

Decimation

Filters

HPF

DRE

INP

INM

Output

Channel

Data to

Audio Bus

Figure 8-7. Signal-Chain Processing Flowchart

The front-end dynamic range enhancer (DRE) gain amplifier in the PCM1822 is very low noise, with a 117-dB

dynamic range performance. Along with a low-noise and low-distortion, multibit, delta-sigma ADC, the front-end

DRE gain amplifier enables the PCM1822 to record a far-field audio signal with very high fidelity, both in quiet

and loud environments. Moreover, the ADC architecture has inherent antialias filtering with a high rejection of

out-of-band frequency noise around multiple modulator frequency components. Therefore, the device prevents

noise from aliasing into the audio band during ADC sampling. Further on in the signal chain, an integrated,

high-performance multistage digital decimation filter sharply cuts off any out-of-band frequency noise with high

stop-band attenuation.

The device supports an input signal bandwidth up to 80 kHz, which allows the high-frequency non-audio signal

to be recorded by using a 176.4-kHz (or higher) sample rate.

www.ti.com

PCM1822

SBASAK0 – DECEMBER 2020 – REVISED MAY 2022

Copyright © 2022 Texas Instruments Incorporated

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Product Folder Links: PCM1822