A7B datasheet(11/23 Pages) ANASEM

11 / 23 page

AnaSem Inc.

Rev. E09-06

A7B Series

Single-cell Li-ion / Li-polymer Battery Protection IC

.......... Future of the analog world

DESCRIPTION OF OPERATION

Normal condition

This IC monitors the battery voltage (VDD) and the voltage of VM terminal, and controls charge and discharge.

If the battery voltage (VDD) is in the range from the over-discharge detection voltage (Vdc) to the over-charge

detection voltage (Vc) and the VM terminal voltage is in the range from the charge over-current detection voltage

(VIc) to the discharge over-current detection voltage (VIdc), this IC turns on both the charge and discharge

control FETs. This state is called the normal condition, and charge and discharge are possible together.

Discharge over-current detection, Load short-circuiting detection

When the discharge current becomes equal to or higher than the specified value under the normal condition, and

if the VM terminal voltage is in the range from the discharge over current detection voltage (VIdc) to the short-

circuiting detection voltage (Vshort) and that state is maintained during more than the discharge over-current

detection delay time (tidc), this IC turns off the discharge control FET to stop discharge. This state is called the

discharge over-current condition.

At that time, if the VM terminal voltage is equal to or higher than Vshort and that state is maintained during more

than the load short-circuiting detection delay time (tshort), this IC turns off the discharge control FET to stop

discharge. This state is called the load short-circuiting detection condition.

While load is connected, in both conditions, the VM terminal voltage equals to VDD potential due to the load, but it

falls by the discharge over-current release resistance (Rdwn) when the load is removed and the resistance

between (+) and (-) terminals of battery pack (refer to “TYPICAL CONNECTION DIAGRAM”) becomes larger

than the value which enables the automatic return.

Then the VM terminal voltage becomes less than VIdc, and if that state is maintained during more than the

release delay time 1 (trel1), this IC returns to normal condition.

Charge over-current detection

When the charge current becomes equal to or higher than the specified value under the normal condition, if the

VM terminal voltage becomes less than the charge over-current detection voltage (VIc) and that state is

maintained during more than the charge over-current detection delay time (tic), this IC turns off the charge

control FET to stop charge. This state is called the charge over-current detection condition.

Then the VM terminal voltage becomes equals to or higher than VIc and that state is maintained during more

than the release delay time 1 (trel1) when the charger is removed and the load is connected, this IC returns to

the normal condition.

If the VM terminal voltage becomes equal to or less than VSS-7V(typical), the charge over-current detection

delay time (tic) changes as below.

8msec model

→

8msec (not changed)

125msec model

→

7msec (typical)

1.0sec model

→ 56msec (typical)

The resistance value between (+) and (-) terminals of battery pack for automatic return changes with battery

voltage (VDD) or VIdc. The standard is expressed with the following equation.

Resistance value for automatic return = Rdwn × (VDD / VIdc - 1)

Note)

A7B Datasheet(PDF) 11 Page - AnaSem Hong Kong Limited.

A7B Datasheet(HTML) 11 Page - AnaSem Hong Kong Limited.

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