ADM2483 datasheet(17/20 Pages) AD

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ADM2483

Rev. 0 | Page 17 of 20

APPLICATIONS INFORMATION

POWER_VALID INPUT

To avoid glitches on outputs A and B caused by slow power-up

and power-down transients on VDD1 (>100 µs/V), the ADM2483

features a power_valid (PV) digital input. This pin should be

driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than

2.0 V, the pin should be driven high. Conversely, upon power-

down, the PV should be driven low before VDD1 reaches 2.0 V.

The power_valid input can be driven, for example, by the

output of a system reset circuit such as the ADM809Z, which

has a threshold voltage of 2.32 V.

VDD1

2.32V

tPOR

2.0V

2.32V

2.0V

RESET

ADM809Z

ADM2483

VDD1

GND1

VDD1

Figure 29. Driving PV with ADM809Z

ISOLATED POWER SUPPLY CIRCUIT

The ADM2483 requires isolated power capable of 5 V at 100 mA,

to be supplied between VDD2 and GND2 pins. If no suitable

integrated power supply is available, then a discrete circuit, such

as the one in Figure 25, can be used. A center tapped transformer

provides electrical isolation. The primary winding is excited

with a pair of square waveforms that are 180° out of phase with

each other. A pair of Schottky diodes and a smoothing capacitor

are used to create a rectified signal from the secondary winding.

The ADP667 linear voltage regulator provides a regulated

power supply to the ADM2483’s bus-side circuitry.

To create the pair of square waves, a D-type flip-flop with

complementary Q/Q outputs is used. The flip-flop can be

connected so that output Q follows the clock input signal. If no

local clock signal is available, then a simple digital oscillator

may be implemented with a hex inverting Schmitt trigger and

resistor and capacitor. In this case, values of 3.9 kV and 1 nF

generate a 364 kHz square wave. A pair of discrete NMOS

transistors, switched by the Q/Q flip-flop outputs, conduct

current through the center tap of the primary transformer

winding in an alternating fashion.

3.9k

Ω

100nF

10nF

74HC14

VCC

74HC74A

CLR

CLK

BS107A

VCC

ISOLATION

BARRIER

SD103C

µF

SD103C

78253

100nF

VCC

OUT

SET

SHDN

GND

ADP667

VDD1

VDD2

GND1

GND2

ADM2483

VCC

Figure 30. Isolated Power Supply Circuit

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