DAC63202 datasheet(12/83 Pages) TI

12 / 83 page

6.15 Timing Requirements: GPIO

all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,

1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, and –40°C ≤ TA ≤ +125°C

MIN

NOM

MAX

UNIT

tGPIHIGH

GPI high time(1)

µs

tGPILOW

GPI low time(1)

µs

tGPAWGD

LDAC falling edge to DAC update delay(2)

µs

tCS2LDAC

SYNC rising edge to LDAC falling edge

µs

tSTP2LDAC

I2C stop bit rising edge to LDAC falling edge

µs

tLDACW

LDAC low time

µs

(1)

The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations. The

actual response time of the GPIO is determined by the delay provided by the configured function and the settling time of the DAC.

(2)

The GPIOs can be configured as channel-specific or global LDAC function.

6.16 Timing Diagrams

SCL

SDA

tBUF

tHDSTA

tLOW

tHDDAT

tHIGH

tSUDAT

tSUSTA

tHDSTA

SUSTO

Low byte ACK cycle

Figure 6-1. I2C Timing Diagram

CSS

SDIS

SDIH

SYNC

SDI

CSHIGH

Bit 23

SCLKLOW

Bit 1

Bit 0

CSH

SCLK

SCLKHIGH

CS2LDAC

LDACW

GPIO/

LDAC

Figure 6-2. SPI Write Timing Diagram

DAC53202, DAC63202

SLASF47 – MAY 2022

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