OPA656 datasheet(10/25 Pages) TI

10 / 25 page

VS+

VIN+

VOUT

Power Supply

ESD Cell

VIN

Internal

Circuitry

Figure 8-3. Internal ESD Protection

8.3.2 Feedback Pin

For high speed analog design, minimizing parasitic capacitances and inductances is critical to get the best

performance from a high-speed amplifier such as the OPA817. Parasitic capacitance and inductance are

especially detrimental in the feedback path and at the inverting input. They result in undesired poles and zeroes

in the feedback that could result in reduced phase margin or instability. Techniques used to correct this phase

margin reduction often result in reduced application bandwidth. To keep system engineers from making these

tradeoff choices and to simplify the PCB layout, OPA817 features an FB pin on the same side as the inverting

input pin (IN–). Figure 8-4 shows how this feature allows for a very short feedback resistor (RF) connection

between the FB and the IN– pin, which minimizes parasitic capacitance and inductance with minimal PCB

design effort. Internally the FB pin is connected to OUT pin through metal routing on the silicon. Due to the fixed

metal sizing of this connection, the FB pin has limited current carrying capability. Therefore, the specifications in

the Absolute Maximum Ratings section must be adhered to for continuous operation. For applications requiring

high accuracy, the metal routing resistance from OUT to FB can be considered and added to RF to set the

desired gain. For more information, see Section 7.5.

INí

IN+

VS+

VSí

OUT

Figure 8-4. RF Connection Between FB and IN– Pins

8.3.3 FET-Input Architecture with Wide Gain-Bandwidth Product

Figure 8-5 shows the open-loop gain and phase response of the OPA817. The GBWP of an op amp is measured

in the 20 dB/decade constant slope region of the AOL magnitude plot. The open-loop gain of 60 dB for the

OPA817 is along this 20 dB/decade slope and the corresponding frequency intercept is at 390 kHz. Converting

60 dB to linear units (1000 V/V) and multiplying it with the 390 kHz frequency intercept gives the GBWP

of OPA817 as 390 MHz. As can be inferred from the AOL Bode plot, the second pole in the AOL response

occurs after AOL magnitude drops below 0 dB (1 V/V). This results in phase change of less than 180° at 0 dB

AOL indicating that the amplifier will be stable in a gain of 1 V/V. Amplifiers like OPA817 that are JFET-input,

low noise and unity-gain stable can be used as high input impedance buffers and gain stages with minimal

degradation in SNR. It has 800 MHz of SSBW in gain of 1V/V configuration with approximately 55° phase

margin.

OPA817

SBOS847 – JULY 2022

www.ti.com

Submit Document Feedback

Product Folder Links: OPA817

OPA656 Datasheet(PDF) 10 Page - Texas Instruments

OPA656 Datasheet(HTML) 10 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Download

Link URL