Figure 9-5 shows the simulated closed-loop bandwidth response of the circuit in Figure 9-4. The circuit was

noise simulation of the TIA circuit. The output-referred voltage noise is shown on the Y-axis to the left, and the

input-referred current noise (which is essentially output-referred voltage noise divided by the transimpedance

gain of 10 kΩ) is shown on the secondary Y-axis to the right.

The flat-band output voltage noise is 13.5 nV/√Hz and is equivalent to 1.35 pA/√Hz of input-referred current

noise. The noise in the relatively low frequency region, where the noise gain of the amplifier is 1 V/V, is

dominated by the thermal noise of the 10 kΩ resistor (12.9 nV/√Hz at 27°C). At mid frequencies beyond the

amplifier's noise starts to become the dominant noise contributor from this frequency onwards before the output

noise starts to roll off at frequencies beyond the 3-dB closed-loop bandwidth. When considering integrated

root-mean-square (RMS) noise, the mid-frequency noise will be a significant contributor; hence, using a 4.5

nV/√Hz low-noise amplifier like OPA817 is advantageous to minimize total RMS noise in the system.

9.2.4 Application Curves

Frequency (Hz)

59

62

65

68

71

74

77

80

83

86

89

100k

1M

10M

100M

D103

Figure 9-5. Closed-Loop Bandwidth of TIA

Frequency (Hz)

10

1

20

2

30

3

50

5

70

7

100

10

200

20

300

30

500

50

700

70

1000

100

10

100

1k

10k

100k

1M

10M

100M

D104

Figure 9-6. Noise Density vs Frequency of TIA

10 Power Supply Recommendations

The OPA817 is intended to operate on supplies ranging from 6 V to 12.6 V. OPA817 supports single-supply,

split, balanced, and unbalanced bipolar supplies. When operating at supplies below 8 V, consideration must be

given to the input common-mode range of the amplifier. Under these supply conditions, the common-mode must

be biased appropriately for linear operation. Thus, the limit to lower supply voltage operation is the usable input

voltage range for the JFET-input stage.

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier like the OPA817 requires careful attention to

board layout parasitics and external component types. Recommendations that will optimize performance include

the following:

1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on

the output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can

react with the source impedance to cause unintentional bandlimiting. Ground and power metal planes act as

one of the plates of a capacitor while the signal trace metal acts as the other separated by PCB dielectric.

To reduce this unwanted capacitance, care must be taken to minimize the routing of the feedback network. A

plane cutout around and underneath the inverting input pin on all ground and power planes is recommended.

Otherwise, ground and power planes should be unbroken elsewhere on the board.

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OPA817

SBOS847 – JULY 2022

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