Pin Description

Pin Name

I/O

Description

VDD

I

VDD is the positive supply to the digital control circuit and other circuitry in LCD bias voltage

generator (Must have same voltage level with VDDA)

RES

I

Active low reset pin; reset all internal status of circuit (Same as power on reset)

VSS

I

VSS is ground

DCOM

I

If pull this pin

²High² then D0~D7 bi-direction bus is used for data transferring; If DCOM pin is

²Low² then D0~D7 bi-direction bus is used for command transferring.

RW

I

If pull this pin high: Indicate we want to read the display data RAM or the internal state. If we

force this to Low: Indicate we want to write data to display data RAM or write some internal

state to registers.

CS

I

This pin is normal low clock input. Data on D0~D7 bi-direction data bus are latched at the fall-

ing edge of CS

D0~D7

B

Those bi-direction pins are used for DATA or command transferring.

CE

I

High input to this pin to enable the control pins on the driver.

OSC1

I

Oscillator input pin.

For internal oscillator mode, this is an input for the internal low power RC oscillator circuit. In

this mode, an external resistor of certain value is placed between the OSC1 and OSC2 pins.

For external oscillator mode, OSC1 pin should be left open

OSC2

O

Oscillator output pin

For internal oscillator mode, this is an output for the internal low power RC oscillator circuit.

External Oscillator input

For external oscillator mode, OSC2 will be an input pin for external clock and no external resis-

tor is needed.

C1P, C1N

¾ If internal DC/DC converter is enabled, a capacitor is required to connect these two pins.

C2P, C2N

¾

If internal tripler is enabled, a capacitor is required to connect these two pins. Otherwise, leave

these pin open.

VLL2~VLL6

O

Group of voltage level pins for driving the LCD panel. They can either be connected to external

driving circuit for external bias supply or connected internally to built-in divider circuit. For in-

ternal voltage divider enable, a 0.1

mF capacitor to VSS is required on each pin.

DUM1, DUM2

O

If internal voltage divider is enable with 1/7 bias selected, a capacitor to VSS is required on

each pin. Otherwise, pull these two pin to VSS

C+, C-

¾ If internal divider circuit is enable, a capacitor is required to connect between these two pin

VCCA1

O

If internal DC/DC Converter is enabled, a 0.1

mF capacitor from this pin to VSS is required. It

can also be an external bias input pin if internal DC/DC converter is not used

VF, VR

¾

This is a feedback path for the gain control (external contrast control) of VLL1 to VLL6. For ad-

justing the LCD driving voltage, it requires a feedback resistor placed between VR and VF, a

gain control resistor placed between VF and VSS, a 10uF capacitor placed between VR and

VSS.

COM0~COM32

O

These pins provide the row driving signal to LCD panel

VDDA

I

VDDA is the positive supply to the noise sensitive circuitry and must have same voltage level

with VDD

ICON1~ICON4

O

There are four independent annunciator driving outputs

IBP

O

This pin combines with ICON1~ICON4 pins to form annunciator driving part.

SEG0~SEG119

O

These 120 pins provide LCD column driving signal to LCD panel.

HT0610

Rev. 1.00

5

February 24, 2004