PCM1820 datasheet(27/44 Pages) TI

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8.3.7 Dynamic Range Enhancer (DRE)

The device integrates an ultra-low noise front-end DRE gain amplifier with 123-dB dynamic range performance

with a low-noise, low-distortion, multibit delta-sigma (ΔΣ) ADC with a 113-dB dynamic range. The dynamic range

enhancer (DRE) is a digitally assisted algorithm to boost the overall channel performance. The DRE monitors

the incoming signal amplitude and accordingly adjusts the internal DRE amplifier gain automatically. The DRE

achieves a complete-channel dynamic range as high as 123 dB. At a system level, the DRE scheme enables

far-field, high-fidelity recording of audio signals in very quiet environments and low-distortion recording in loud

environments.

The DRE can be enabled only in slave mode by driving the MD1 pin high. Table 8-20 shows the DRE selection

for the record channel. Additionally, this feature is only supported in the PCM1820-Q1 and not in the PCM1821-

Q1.

Table 8-20. DRE Selection for the Record Channel

MD1

DRE SELECTION (Supported Only in Slave Mode)

Low

The DRE is disabled in slave mode. For master mode, the DRE is always disabled.

High

The DRE is enabled with DRE_LVL = –36 dB and DRE_MAXGAIN = 24 dB in slave mode.

For master mode, the DRE is always disabled.

This algorithm is implemented with very low latency and all signal chain blocks are designed to minimize

any audible artifacts that may occur resulting from dynamic gain modulation. The target signal threshold level

(DRE_LVL), at which the DRE is triggered, is fixed to the –36-dB input signal level. The DRE gain range can be

dynamically modulated by using DRE_MAXGAIN, which is fixed to 24 dB to maximize the benefit of the DRE in

real-world applications and to minimize any audible artifacts.

Enabling the DRE for processing increases the power consumption of the device because of increased

signal processing. Therefore, disable the DRE for low-power critical applications. Furthermore, the DRE is not

supported for output sample rates greater than 48 kHz.

8.4 Device Functional Modes

8.4.1 Active Mode

The device wakes up in active mode when AVDD and IOVDD are available. Configure all hardware control pins

(MSZ, MD0, MD1, and FMT0 ) for the device desired mode of operation before enabling clocks for the device.

In active mode, when the audio clocks are available, the device automatically powers up all ADC channels and

starts transmitting data over the audio serial interface. If the clocks are stopped, then the device auto powers

down the ADC channels.

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PCM1820-Q1, PCM1821-Q1

SBASAH4A – APRIL 2022 – REVISED SEPTEMBER 2022

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Product Folder Links: PCM1820-Q1 PCM1821-Q1

PCM1820 Datasheet(PDF) 27 Page - Texas Instruments