PCM1820 datasheet(29/44 Pages) TI

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9.2.1 Design Requirements

Table 9-1 lists the design parameters for this application.

Table 9-1. Design Parameters

KEY PARAMETER

SPECIFICATION: 3.3-V AVDD OPERATION

AVDD

3.3 V

AVDD supply current consumption

12.9 mA (two-channel recording, fS = 48 kHz)

IOVDD

1.8 V or 3.3 V

9.2.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCM182(0/1)-Q1 for this specific application. The

following steps provide a sequence of steps that must be executed in the time between powering the device up

and reading data from the device or transitioning from one mode to another mode of operation.

1. Apply power to the device:

a. Power-up the IOVDD and AVDD power supplies

b. The device now goes into low-power mode

2. Configure the pins for correct configuration:

a. Connect the MSZ, FMT0, MD0, and MD1 pin voltages for the desired configuration

b. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the

BCLK to FSYNC ratio

c. The device recording data are now sent to the host processor via the audio serial data bus

3. Stop the clocks to stop recording of data at any time

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PCM1820-Q1, PCM1821-Q1

SBASAH4A – APRIL 2022 – REVISED SEPTEMBER 2022

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Product Folder Links: PCM1820-Q1 PCM1821-Q1

PCM1820 Datasheet(PDF) 29 Page - Texas Instruments