AX88195P datasheet(10/37 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88195 Local CPU Bus Fast Ethernet MAC Controller

2.0 Signal Description

The following terms describe the AX88195 pin-out:

All pin names with the “/” suffix are asserted low.

The following abbreviations are used in following Tables.

Input

Pull Up

Output

Pull Down

I/O

Input/Output

Power Pin

Open Drain

2.1 Local CPU Bus Interface Signals Group

SIGNAL

TYPE

PIN NO.

DESCRIPTION

SAL[2:0]

I/PD

113 – 111

System Address Select Low : Signals SAL[2:0] are additional address

signal input lines which active low enable higher I/O address decoder

on chip.

SAH[2:0]

I/PU

116 – 114

System Address Select High : Signals SAH[2:0] are additional

address signal input lines which active high enable higher I/O

address decoder on chip.

SAX[3:0]

I/PU

122 – 121

118 – 117

System Address Select Low/High : Signals SAX[3:0] are additional

address signal input lines which active low/high depend on power on

setting to enable higher I/O address decoder on chip.

SA[9:1],

SA[0]/UDS

10 – 1

System Address : Signals SA[9:0] are address bus input lines which

lower I/O spaces on chip. SA[0] also means Upper Data Strobe

(/UDS) active low signal in 68K application mode.

/BHE

/LDS

Bus High Enable or Lower Data Strobe : Bus High Enable is active

low signal in some 16 bit application mode which enable high bus

(SD[15:8]) active. The signal also name as Lower Data Strobe (/LDS)

for 68K application mode.

SD[15:0]

I/O

20 – 23,

25 – 28,

30 – 33,

35 – 38

System Data Bus : Signals SD[15:0] constitute the bi-directional

data bus.

IREQ/IREQ

Interrupt Request : When ISA BUS or 80186 CPU mode is select.

IREQ is asserted high to indicate the host system that the chip

requires host software service. When MC68K or MCS-51 CPU

mode is select. /IREQ is asserted low to indicate the host system that

the chip requires host software service.

RDY/DTACK

125

Ready : This signal is set low to insert wait states during Remote

DMA transfer.

/Dtack : When Motorola CPU type is select, the pin is active low

inform CPU that data is accepted.

/CS

123

Chip Select

When the /CS signal is asserted, the chip is selected.

/IORD

I/O Read :The host asserts /IORD to read data from AX88195 I/O

space. When Motorola CPU type is select , the pin is useless.

/IOWR

R/W

I/O Write :The host asserts /IOWR to write data into AX88195 I/O

space. When Motorola CPU type is select, the pin is active high for

read operation at the same time.

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