AX88195P datasheet(3/37 Pages) ASIX

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ASIX ELECTRONICS CORPORATION

AX88195 Local CPU Bus Fast Ethernet MAC Controller

6.4.5 68K Type I/O Access Timing .................................................................................................................... 27

6.4.6 8051 Bus Access Timing........................................................................................................................... 28

6.4.7 MII Timing............................................................................................................................................... 29

6.4.8 Asynchronous Memory I/F Access Timing ................................................................................................ 30

7.0 PACKAGE INFORMATION........................................................................................................................... 31

APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 32

A.1 USING CRYSTAL.............................................................................................................................................. 32

A.2 USING OSCILLATOR......................................................................................................................................... 32

A.3 DUAL POWER (5V AND 3.3V/3.0V) APPLICATION ............................................................................................. 33

A.4 SINGLE POWER (3.3V/3.0V) APPLICATION ........................................................................................................ 33

A.5 DUAL POWER (5V AND 3.3V) APPLICATION WITH 3.3V PHY............................................................................. 34

APPENDIX B: APPLICATION NOTE 2 ............................................................................................................. 35

B.1 ADVANCE APPLICATION FOR USING CRYSTAL................................................................................................... 35

APPENDIX C: APPLICATION NOTE FOR RDY IS NOT APPLICABLE ...................................................... 36

ERRATA OF AX88195 V1..................................................................................................................................... 37

FIGURES

FIG - 1 AX88195 BLOCK DIAGRAM ............................................................................................................................. 4

FIG - 2 AX88195 PIN CONNECTION DIAGRAM.............................................................................................................. 5

FIG - 3 AX88195 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ............................................................................... 6

FIG - 4 AX88195 PIN CONNECTION DIAGRAM FOR 80X86 MODE .................................................................................. 7

FIG - 5 AX88195 PIN CONNECTION DIAGRAM FOR MC68K MODE................................................................................ 8

FIG - 6 AX88195 PIN CONNECTION DIAGRAM FOR MCS-51 MODE ............................................................................... 9

TABLES

TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP .................................................................................................. 11

TAB - 2 MII INTERFACE SIGNALS GROUP..................................................................................................................... 11

TAB - 3 EEPROM BUS INTERFACE SIGNALS GROUP ..................................................................................................... 12

TAB - 4 SRAM INTERFACE PINS GROUP ...................................................................................................................... 12

TAB - 5 MISCELLANEOUS PINS GROUP......................................................................................................................... 13

TAB - 6 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 13

TAB - 7 I/O ADDRESS MAPPING ................................................................................................................................. 14

TAB - 8 LOCAL MEMORY MAPPING ............................................................................................................................ 14

TAB - 9 PAGE 0 OF MAC CORE REGISTERS MAPPING.................................................................................................. 15

TAB - 10 PAGE 1 OF MAC CORE REGISTERS MAPPING................................................................................................ 16

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