6.5 Thermal Information (continued)

THERMAL METRIC(1)

ESD752

ESD762

UNIT

DBZ (SOT-23)

DCK (SOT-323 / SC-70)

DBZ (SOT-23)

3 PINS

3 PINS

3 PINS

RθJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

N/A

N/A

°C/W

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.6 Electrical Characteristics

over TA = 25°C (unless otherwise noted)(1)

PARAMETER

TEST CONDITIONS

DEVICE

MIN

TYP

MAX UNIT

VRWM

Reverse stand-off voltage

–24

24

V

VBRF

Forward breakdown voltage(2)

IIO = 10 mA, IO to GND

25.5

35.5

V

VBRR

Reverse breakdown voltage(2)

IIO = –10 mA, IO to GND

–35.5

–25.5

V

VCLAMP Clamping voltage(3)

IPP = 5.7 A, tp = 8/20 µs, IO to GND

ESD752

37

V

IPP = 2.5 A, tp = 8/20 µs, from IO to GND

ESD762

36

V

VCLAMP Clamping voltage(4)

IPP = 16 A, TLP, IO to GND or GND to IO

ESD752

35

V

ESD762

38

V

VHold

Holding voltage after snapback(5) TLP

ESD752

30

V

ESD762

30

V

ILEAK

Leakage current

VIO = ±24 V, IO to GND

-50

5

50

nA

RDYN

Dynamic resistance(4)

IO to GND and GND to IO

ESD752

0.35

Ω

ESD762

0.57

Ω

CL

Line capacitance(6)

VIO = 0 V, f = 1 MHz, Vpp = 30 mV

ESD752

3

5

pF

ESD762

1.7

2.8

pF

(1)

Measurements made on each IO channel.

(2)

VBRF and VBRR are defined as the voltage when +/- 10 mA is applied in the positive or negative direction respectively, before the device

latches into the snapback state.

(3)

Device stressed with 8/20 μs exponential decay waveform according to IEC 61000-4-5.

(4)

Non-repetitive current pulse, Transmission Line Pulse (TLP); square pulse; ANSI / ESD STM5.5.1-2008

(5)

VHOLD is defined as the lowest voltage on the TLP plot once the trigger threshold is reached and the device snapbacks and begins

clamping the voltage.

(6)

Measured from IO to GND on each channel.

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ESD752, ESD762

SLVSGX0B – MAY 2022 – REVISED NOVEMBER 2022

Copyright © 2022 Texas Instruments Incorporated

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