The low input offset voltage and offset voltage drift of OPA817 makes it a very suitable amplifier for high

precision, high input impedance, wideband data acquisition system front-ends. As Figure 9-2 shows, the system

benefits from the low noise JFET input stage with pico-amperes of input bias current to achieve higher precision

at 1-MΩ input impedance settings and higher SNR at 50-Ω input impedance setting simultaneously in a typical

data acquisition front-end circuit.

Frequency (Hz)

-20

-195

-10

-180

0

-165

10

-150

20

-135

30

-120

40

-105

50

-90

60

-75

70

-60

80

-45

90

-30

100

-15

110

0

120

15

1k

10k

100k

1M

10M

100M

1G

AOL Magnitude (dB)

AOL Phase ()

RL = 100 Ω

Figure 8-5. Open-Loop Gain Magnitude and Phase

Vs Frequency

Frequency (Hz)

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

110

120

1k

10k

100k

1M

10M

100M

1G

TA = −40C

TA = 25 C

TA = 105 C

RL = 100 Ω

Figure 8-6. Open-Loop Gain Magnitude vs

Temperature

8.3.4 Device Functional Modes

8.3.4.1 Power-Down (PD) Pin

The OPA817 includes a power-down mode for low-power or standby operation and only consumes 55 μA

(typical) of current when placed in power-down mode. Low-power systems that are only active for small periods

of time benefit from this feature. The OPA817 can transition from low-power mode to active-mode in 300

ns (typical). For power-down pin control thresholds, refer to Section 7.5. An internal pull-up resistor of 2-MΩ

provides a weak pull-up to VS+ if PD is left unconnected. An external 1-nF capacitor to VS+ may be used to avoid

external noise coupling and false triggering. If the power-down mode is not used in an application, then connect

the PD pin to VS+.

OPA817

SBOS847A – JULY 2022 – REVISED DECEMBER 2022

www.ti.com

16

Submit Document Feedback

Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: OPA817