• Optimizing Overshoot: The OPA817 features an internal slew-boost circuit to deliver fast rise-time

in applications needing high slew rates such as when configured as a transimpedance amplifier. For

applications where overshoot needs to be limited, the input slew rates can be limited with introducing a series

resistance (RS) as shown in Figure 9-3. The resistance RS forms a low pass filter with the input capacitance

of approximately 2.6 pF at the noninverting pin of the OPA817 limiting the input slew rate to the amplifier.

Figure 9-4 shows how limiting the input slew rate to the amplifier results in good overshoot performance, and

Figure 9-5 shows how this achieves a small signal and large signal bandwidth of 200 MHz.

9.2.4 Application Curves

Time (ns)

10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

D105

VIN =  0.5 V-step

VOUT, RS = 0 

VOUT, RS = 250 

Figure 9-4. Step Response of Digitizer Front-End

Frequency (Hz)

-15

-12

-9

-6

-3

0

3

100k

1M

10M

100M

1G

D106

VOUT = 100 mVPP

VOUT = 1 VPP

Figure 9-5. Frequency Response for RS = 250 Ω

10 Power Supply Recommendations

The OPA817 is intended to operate on supplies ranging from 6 V to 12.6 V. OPA817 supports single-supply,

split, balanced, and unbalanced bipolar supplies. When operating at supplies below 8 V, consideration must be

given to the input common-mode range of the amplifier. Under these supply conditions, the common-mode must

be biased appropriately for linear operation. Thus, the limit to lower supply voltage operation is the usable input

voltage range for the JFET-input stage.

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier like the OPA817 requires careful attention to

board layout parasitics and external component types. Recommendations that will optimize performance include

the following:

1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on

the output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance can

react with the source impedance to cause unintentional bandlimiting. Ground and power metal planes act as

one of the plates of a capacitor while the signal trace metal acts as the other separated by PCB dielectric.

To reduce this unwanted capacitance, care must be taken to minimize the routing of the feedback network. A

plane cutout around and underneath the inverting input pin on all ground and power planes is recommended.

Otherwise, ground and power planes should be unbroken elsewhere on the board.

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OPA817

SBOS847A – JULY 2022 – REVISED DECEMBER 2022

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