MAX2 datasheet(45/297 Pages) ALTERA

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Chapter 2: MAX II Architecture

2–23

I/O Structure

Altera Corporation

MAX II Device Handbook

I/O Structure

IOEs support many features, including:

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LVTTL and LVCMOS I/O standards

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3.3-V, 32-bit, 66-MHz PCI compliance

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Joint Test Action Group (JTAG) boundary-scan test (BST) support

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Programmable drive strength control

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Weak pull-up resistors during power-up and in system programming

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Slew-rate control

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Tri-state buffers with individual output enable control

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Bus-hold circuitry

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Programmable pull-up resistors in user mode

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Unique output enable per pin

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Open-drain outputs

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Schmitt trigger inputs

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Fast I/O connection

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Programmable input delay

MAX II device IOEs contain a bidirectional I/O buffer. Figure 2–19 shows the MAX II

IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s

bidirectional I/O buffers. The Quartus II software automatically attempts to place

registers in the adjacent LAB with fast I/O connection to achieve the fastest possible

clock-to-output and registered output enable timing. For input registers, the

Quartus II software automatically routes the register to guarantee zero hold time.

You can set timing assignments in the Quartus II software to achieve desired I/O

timing.

Fast I/O Connection

A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O

block provides faster output delays for clock-to-output and t

PD propagation delays.

This connection exists for data output signals, not output enable signals or input

signals. Figure 2–20, Figure 2–21, and Figure 2–22 illustrate the fast I/O connection.

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