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MAX2 Datasheet(PDF) 93 Page - Altera Corporation |
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MAX2 Datasheet(HTML) 93 Page - Altera Corporation |
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93 / 297 page  Chapter 5: DC and Switching Characteristics 5–21 Timing Model and Specifications © August 2009 Altera Corporation MAX II Device Handbook Table 5–26 shows the external I/O timing parameters for EPM2210 devices. External Timing I/O Delay Adders The I/O delay timing parameters for I/O standard input and output adders, and input delays are specified by speed grade independent of device density. Table 5–27 through Table 5–31 show the adder delays associated with I/O pins for all packages. The delay numbers for –3, –4, and –5 speed grades shown in Table 5–27 through Table 5–33 are based on an EPM1270 device target, while –6, –7, and –8 speed grade values are based on an EPM570Z device target. If an I/O standard other than 3.3-V LVTTL is selected, add the input delay adder to the external t SU timing parameters shown in Table 5–23 through Table 5–26. If an I/O standard other than 3.3-V LVTTL with 16 mA drive strength and fast slew rate is selected, add the output delay adder to the external t CO and tPD shown in Table 5–23 through Table 5–26. Table 5–26. EPM2210 Global Clock External I/O Timing Parameters Symbol Parameter Condition MAX II / MAX IIG Unit –3 Speed Grade –4 Speed Grade –5 Speed Grade MinMax MinMax MinMax t PD1 Worst case pin-to-pin delay through 1 look-up table (LUT) 10 pF —7.0 —9.1 — 11.2 ns t PD2 Best case pin-to-pin delay through 1 LUT 10 pF —3.7 —4.8 —5.9 ns t SU Global clock setup time — 1.2 — 1.5 — 1.9 — ns t H Global clock hold time — 0 — 0 — 0 — ns t CO Global clock to output delay 10 pF 2.0 4.6 2.0 6.0 2.0 7.4 ns t CH Global clock high time — 166 — 216 — 266 — ps t CL Global clock low time — 166 — 216 — 266 — ps t CNT Minimum global clock period for 16-bit counter — 3.3 — 4.0 — 5.0 — ns f CNT Maximum global clock frequency for 16-bit counter — — 304.0 (1) —247.5 — 201.1 MHz Note to Table 5–26: (1) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay performs faster than this global clock input pin maximum frequency. Table 5–27. External Timing Input Delay Adders (Part 1 of 2) I/O Standard MAX II / MAX IIG MAX IIZ Unit –3 Speed Grade –4 Speed Grade –5 Speed Grade –6 Speed Grade –7 Speed Grade –8 Speed Grade Min Max Min Max Min Max Min Max Min Max Min Max 3.3-V LVTTL Without Schmitt Trigger —0 —0 — 0 —0 — 0 — 0 ps With Schmitt Trigger — 334 — 434 — 535 — 387 — 434 — 442 ps |
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