 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MAX2 Datasheet(PDF) 39 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
MAX2 Datasheet(HTML) 39 Page - Altera Corporation |
|
|
39 / 297 page  Chapter 2: MAX II Architecture 2–17 Global Signals © October 2008 Altera Corporation MAX II Device Handbook The global clock network drives to individual LAB column signals, LAB column clocks [3..0], that span an entire LAB column from the top to the bottom of the device. Unused global clocks or control signals in a LAB column are turned off at the LAB column clock buffers shown in Figure 2–14. The LAB column clocks [3..0] are multiplexed down to two LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. See “LAB Control Signals” on page 2–5 for more information. Figure 2–13. Global Clock Generation Note to Figure 2–13 : (1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal. 4 4 GCLK0 Global Clock Network GCLK1 GCLK2 GCLK3 Logic Array(1) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
