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Chapter 2: MAX II Architecture

Global Signals

MAX II Device Handbook

Altera Corporation

The UFM block communicates with the logic array similar to LAB-to-LAB interfaces.

The UFM block connects to row and column interconnects and has local interconnect

regions driven by row and column interconnects. This block also has DirectLink

interconnects for fast connections to and from a neighboring LAB. For more

information about the UFM interface to the logic array, see “User Flash Memory

Block” on page 2–18.

Table 2–2 shows the MAX II device routing scheme.

Global Signals

Each MAX II device has four dual-purpose dedicated clock pins (GCLK[3..0], two

pins on the left side and two pins on the right side) that drive the global clock network

for clocking, as shown in Figure 2–13. These four pins can also be used as general-

purpose I/O if they are not used to drive the global clock network.

The four global clock lines in the global clock network drive throughout the entire

device. The global clock network can provide clocks for all resources within the

device including LEs, LAB local interconnect, IOEs, and the UFM block. The global

clock lines can also be used for global control signals, such as clock enables,

synchronous or asynchronous clears, presets, output enables, or protocol control

signals such as TRDY and IRDY for PCI. Internal logic can drive the global clock

network for internally-generated global clocks and control signals. Figure 2–13 shows

the various sources that drive the global clock network.

Table 2–2. MAX II Device Routing Scheme

Source

Destination

LUT

Chain

Local

(1)

DirectLink

(1)

R4 (1)

C4 (1)

UFM

Block

Column

IOE

Row

IOE

Fast I/O

(1)

LUT Chain

—

——

—

——

—

Local

Interconnect

——

—

DirectLink

Interconnect

——

—

———

—

R4 Interconnect

—

——

—

C4 Interconnect

—

——

—

——

UFM Block

—

——

—

Column IOE

—

——

—

Row IOE

—

——

—

Note to Table 2–2:

(1) These categories are interconnects.

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