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MAX2 Datasheet(PDF) 87 Page - Altera Corporation |
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MAX2 Datasheet(HTML) 87 Page - Altera Corporation |
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87 / 297 page  Chapter 5: DC and Switching Characteristics 5–15 Timing Model and Specifications © August 2009 Altera Corporation MAX II Device Handbook t DDS Data register data in setup to data register clock 20 — 20 — 20 — 20 — 20 — 20 — ns t DDH Data register data in hold from data register clock 20 — 20 — 20 — 20 — 20 — 20 — ns t DP Program signal to data clock hold time 0 — 0 — 0 — 0— 0— 0 — ns t PB Maximum delay between program rising edge to UFM busy signal rising edge — 960 — 960 — 960 — 960 — 960 — 960 ns t BP Minimum delay allowed from UFM busy signal going low to program signal going low 20 — 20 — 20 — 20 — 20 — 20 — ns t PP M X Maximum length of busy pulse during a program — 100 — 100 — 100 — 100 — 100 — 100 µs t AE Minimum erase signal to address clock hold time 0 — 0 — 0 —0 — 0 —0 — ns t EB Maximum delay between the erase rising edge to the UFM busy signal rising edge — 960 — 960 — 960 — 960 — 960 — 960 ns t BE Minimum delay allowed from the UFM busy signal going low to erase signal going low 20 — 20 — 20 — 20 — 20 — 20 — ns t EPM X Maximum length of busy pulse during an erase — 500 — 500 — 500 — 500 — 500 — 500 ms t DCO Delay from data register clock to data register output — 5 — 5 — 5 —5 —5 —5 ns Table 5–21. UFM Block Internal Timing Microparameters (Part 2 of 3) Symbol Parameter MAX II / MAX IIG MAX IIZ Unit –3 Speed Grade –4 Speed Grade –5 Speed Grade –6 Speed Grade –7 Speed Grade –8 Speed Grade Min Max Min Max Min Max Min Max Min Max Min Max |
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