8.3.8 Integrated Surge Protection and Transient Waveform Tolerance

The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC

61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100

nF supply decoupling capacitor between VCC and GND, and 1 µF between VCC_IN/OUT and GND.

External TVS diodes may be required for higher transient protection levels. The system designer should ensure

that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The

device is capable of withstanding up to ±65-V transient pulses < 100 µs.

Decoupling

Network

R

EUT

VCC

GND

OUT

>100nF

Combination

Wave

Generator

1.2/50 - 80/20 µs CWG

R = 500 Ω

Figure 8-6. Surge Test Setup

8.3.9 Power Up Sequence

VCC_IN and VCC domains can be powered up in any sequence. In the event of VCC is powered and VCC_IN is

not, the OUT pin remains in high impedance.

8.3.10 Undervoltage Lock-Out (UVLO)

The device enters UVLO if the VCC voltage falls below V(UVLO). (For the device without the integrated LDO, the

device monitors VCC_IN in addition to VCC. UVLO happens if either supply falls below the threshold.)

As soon as the supply falls below V(UVLO), NFAULT is pulled low, the LDO is turned off and the OUT output is

disabled (Hi-Z). Receiver performance is not specified in this mode.

When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present) and the

LDO will be enabled immediately. The OUT output will be turned on after T(UVLO) delay.

8.4 Device Functional Modes

These devices can operate in three different modes.

8.4.1 NPN Configuration (N-Switch Mode)

Set IN pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side

configuration) on OUT.

8.4.2 PNP Configuration (P-Switch Mode)

Set IN pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on OUT.

8.4.3 Push-Pull Mode

Set EN pin high and toggle IN as control for realizing the function of a push-pull output on OUT. Table 8-5, Table

8-6, and Table 8-7 summarize the pin configurations to accomplish the functional modes.

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SLLSFL4A – FEBRUARY 2022 – REVISED DECEMBER 2022

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