11 Layout

11.1 Layout Guidelines

• Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,

layer 2 as GND, layer 3 for the 24-V supply plane (VCC), and layer 4 for the regulated output supply

(VCC_IN/OUT).

• Connect the thermal pad to GND with maximum amount of thermal vias for best thermal performance.

• Use entire planes for VCC, VCC_IN/OUT and GND to assure minimum inductance.

• The VCC terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor with a

minimum value of 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending

on max sensor supply fault rating) and an X5R or X7R dielectric.

• • The optimum placement of the capacitor is closest to the VCC and GND terminals to reduce supply drops

during large supply current loads. See Figure 11-1 for a PCB layout example.

• Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a

defined voltage potential to the system controller inputs when the outputs are high-impedance.

• Connect the RSET resistor between ILIM_ADJ and GND.

• Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, 1 μF, ceramic decoupling

capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.

11.2 Layout Example

VCC

NFAULT

1uF/10V

100nF/

50V

RSET

Exposed Thermal

Pad Area

VIA to Layer 2: Power Ground Plane (VCC)

VIA to Layer 3: 24V Supply Plane (GND)

VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)

OUT

GND

VCC

OUT

GND

IN

EN

Use Multiple Vias for

VCC and GND

NC

NC

Figure 11-1. Layout Example

TIOS102, TIOS1023, TIOS1025

SLLSFL4A – FEBRUARY 2022 – REVISED DECEMBER 2022

www.ti.com

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