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AP39811 Datasheet(PDF) 13 Page - Diodes Incorporated

Part # AP39811
Description  PRIMARY SIDE REGULATED POWER SWITCHER FOR SLANT IV CURVE
PDF  18 Pages
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Manufacturer  DIODES [Diodes Incorporated]
Direct Link  http://www.diodes.com
Logo DIODES - Diodes Incorporated

AP39811 Datasheet(HTML) 13 Page - Diodes Incorporated

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AP39811
Document number: DS39992 Rev. 5 - 2
13 of 18
www.diodes.com
June 2019
© Diodes Incorporated
AP39811
Operation Description (continued)
Figure 6: VCS and fS Versus Io
7.
Leading Edge Blanking
When the power switch is turned on, a turn-on spike will occur on the VCS sense resistance. To avoid false-termination of the switching pulse, a
300ns leading-edge blanking is built in. During this blanking period, the current sense comparator is disabled and the primary MOSFET cannot be
turned off.
8.
Valley Turn-on
When the off time (tOFF) is shorter than tVAL-ON, the AP39811 power system can work with valley turn-on. It can reduce the switching-on power
losses and achieve high overall efficiency. At the same time, because of valley turn-on the switching frequency has the random jitter feature,
which will be benefitial to conductive EMI performance. And valley turn-on can also reduce the power switch turn-on spike current and then
achieve the better radioactive EMI performance.
9.
VCS Jitter
Even though the valley turn-on function produces the random frequency jitter feature, an active frequency jitter function is added in the AP39811.
The active frequency dithering is realized by applying variation on VCS reference (VCS_REF). The VCS_REF is changed every 2 cycles and the period
of variation is 12 cycles, which is shown as Figure 7. The variation between VCS4 and VCS1 is +/-3% using the mean level as a reference.
Figure 7: VCS Jitter
10. Adjustable Line Compensation
In real system, there exists a delay time, from the VSOURCE reach the inner VCS threshold to the actual switch turn-off point. The delay time
contains the propagation time of the inner comparator and the driver delay, and it does not change with line voltage. The delay time leads to
different primary peak current under different line voltage, which results in different output current in CC mode.
VCS1
VCS2
VCS3
VCS4
VCS3
VCS2
VCS1
VCS2
VCS3
VCS4
VCS3
VCS2
VCS1
Mean Level
AM
FM
FM
kHz
100%
33%
3%
Vo
VCS_H
20
VCS_L
IO/IO_CC



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