ISL68227IRAZ datasheet(30/100 Pages) RENESAS

30 / 100 page

ISL68227

7. Layout and Design Considerations

FN9333 Rev.1.00

Page 30 of 99

Oct.1.20

Layout and Design Considerations

The following layout and design strategies help minimize noise coupling and the impact of board parasitic

impedances on converter performance, and they optimize the heat dissipating capabilities of the Printed Circuit

Board (PCB). Follow these practices during the layout and design process.

7.1

Pin Noise Sensitivity, Design, and Layout Consideration

Table 5 provides general guidance on best practices related to pin noise sensitivity. Use of good engineering

judgment is required to implement designs based on criteria specific to the situation.

Table 5.

Pin Design and/or Layout Consideration

Pin Name

Noise

Sensitive

Description

VINSEN

Yes

Filter VINSEN with 100nF capacitor when sensing VIN directly. Use 10nF when using a resistor divider.

RGNDx

VSENx

Yes

Treat each of the remote voltage sense pairs as differential signals in the PCB layout. Route them side

by side on the same layer. Do not route them in proximity to noisy signals like PWM or Phase. Place a

3.3nF capacitor across the signals directly at the pins on the top layer.

PGx

Open-drain. Avoid setting its pull-up higher than VCC. Tie it to ground when not used.

PMSCL,

PMSDA,

nPMALERT

Yes

50kHz to 2MHz signals should pair up with nPMALERT and be routed carefully between devices and

back to the host. Provide 20 mils of spacing within PMSDA, nPMALERT, and PMSCL, and more than

30 mils to all other signals. See the SMBus design guidelines and place proper terminated (pull-up)

resistance for impedance matching. Tie to ground when not used. Pull up to 3.3V max.

TEMPx

Yes

While using SPS, place a filter capacitor no greater than 500pF between each TEMP pin and ground

near the IC. While using NTC, place a 47pF capacitor and a 22k resistor near the IC and route a

differential signal pair from there to the remote NTC. Use Murata NCP15XH103J03RC (5% tolerance) or

NCP15XH103F03RC (1% tolerance). Tie to ground if not used.

nVRHOT

Open drain. Avoid setting its pull-up rail higher than VCC.

VCC

Yes

Place a 1µF MLCC decoupling capacitor (X5R or better) directly at the pin.

VCCS

Yes

Place a 4.7µF MLCC decoupling capacitor (X5R or better) directly at the pin.

PWMx

Avoid routing near noise sensitive analog lines such as current sense or voltage sense. Leave floating if

not used.

CSx

CSRTNx

Yes

Treat each of the current sense pairs as differential signals in the PCB layout. Route them side by side on

the same layer. Do not route them in close proximity to noisy signals like PWM or Phase. Proper routing

of current sense is perhaps the most critical of all the layout tasks. Place the R-C filter between CSx and

CSRTNx at the controller for SPS configuration.

GND

Yes

This EPAD is the ground for all IC signals. Use four or more vias to directly connect the EPAD to the

ground plane. Never use only a single via or a 0Ω resistor connection to the power ground plane. Split

ground planes are not advised.

General

Comments

The layer next to the top or bottom layer should be a ground layer. The signal layers should be

sandwiched between the ground layers if possible.

ISL68227IRAZ Datasheet(PDF) 30 Page - Renesas Technology Corp

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