EM78P451WM datasheet(40/54 Pages) EMC

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EM78P451

8-Bit Microcontroller with OTP ROM

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Product Specification (V1.1) 06.30.2003

(This specification is subject to change without further notice)

X: Not used. U: Unknown or don’t care.P: Previous value before reset.

t : Check Table 7

4.7.1 The Status of RST, T, and P of STATUS Register

A RESET condition is initiated by the following events:

1. A power-on condition,

2. Watchdog timer time-out.

The values of T and P, listed in Table 7 are used to check how the processor wakes up.

Table 8 shows the events that may affect the status of T and P.

Table 7 The Values of RST, T and P After RESET

Reset Type

Power on

WDT during Operating mode

WDT wake-up during SLEEP1 mode

WDT wake-up during SLEEP2 mode

Wake-Up on pin change during SLEEP2 mode

P: Previous value before reset

Table 8 The Status of RST, T and P Being Affected by Events

Event

Power on

WDTC instruction

WDT time-out

SLEP instruction

Wake-Up on pin change during SLEEP2 mode

P: Previous value before reset

4.8 Interrupt

The EM78P451 has the following interrupts.

1. /TCC overflow interrupt

2. External interrupt (/INT)

3. Serial Peripheral Interface (SPI) transmission completed interrupt.

4. Timer1 comparator completed interrupt.

R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF

is the interrupt mask register. Global interrupt is enabled by ENI instruction and is

disabled by DISI instruction. When one of the interrupts (if enabled) is generated, will

cause the next instruction to be fetched from address 001H. Once in the interrupt

service routine the source of the interrupt can be determined by polling the flag bits in

EM78P451WM Datasheet(PDF) 40 Page - ELAN Microelectronics Corp