EM78P451WM datasheet(15/54 Pages) EMC

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EM78P451

8-Bit Microcontroller with OTP ROM

Product Specification (V1.1) 06.30.2003

• 11

(This specification is subject to change without further notice)

Bit 6 (INT)

An interrupt enable flag cannot be written by the CONTW instruction.

0: interrupt masked by the DISI instruction.

1: interrupt enabled by the ENI or RETI instruction.

Bit4, 5

Not used, and to be read as “0”.

Bit 3 (PAB)

Prescaler assignment bit.

0: TCC

1: WDT

Bit 0 (PSR0) ~ Bit 2 (PSR2)

TCC/WDT prescaler bits.

PSR2

PSR1

PSR0

TCC Rate

WDT Rate

1:2

1:1

1:4

1:2

1:8

1:4

1:16

1:8

1:32

1:16

1:64

1:32

1:128

1:64

1:256

1:128

Bits 0~3, and 7

of the CONT register are readable and writable.

4.2.3 IOC5 ~ IOC9 (I/O Port Control Register)

"1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as

output.

Both P74 and P76 should not be defined as output pins at the same time. This also

applies to both P75 and P77.

Only the lower 6 bits of the IOC9 register are used.

4.2.4 IOCC (T1CON: Timer1 Control Register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0C

T1CON/IOCC

TM1E TM1P1 TM1P0

TM1E (bit2):

Timer1 Function Enable bit

1 = Enable timer1 function.

0 = Disable timer1 function as default.

TM1P (bit1~bit0):

Timer1 Prescaler bit

Timer1 prescaler table for FOSC will be illustrated in the Section on

Timer1 in later pages.

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