EM78P451WM datasheet(14/54 Pages) EMC

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EM78P451

8-Bit Microcontroller with OTP ROM

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Product Specification (V1.1) 06.30.2003

(This specification is subject to change without further notice)

4.1.13 RF (PWP: Pulse width preset register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0F

PWP/RF PWP7

PWP6

PWP5

PWP4

PWP3

PWP2

PWP1

PWP0

PWP7~PWP0 is bit set of pulse width preset in advance for the desired width of baud

clock.

4.1.14 R20~R3E (General Purpose Register)

RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.

4.1.15 R3F (Interrupt Status Register)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x3F

ISR/R3F

TM1IF

SPIIF

EXIF

TCIF

Bit 0 (TCIF)

the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared

by software.

Bit 1 (EXIF)

External interrupt flag. Set by falling edge on /INT pin, flag cleared by

software

Bit 2 (SPIIF)

SPI interrupt flag. Set by data transmission complete, flag cleared by

software.

Bit 3 (TM1IF)

Timer1 interrupt flag. Set by the comparator at Timer1 application, flag

cleared by software.

Bits 2~7

are not used and read as “0”.

"1" means interrupt request, "0" means non-interrupt.

R3F can be cleared by instruction, but cannot be set by instruction.

IOCF is the interrupt mask register.

Note that to read R3F will result to "logic AND" of R3F and IOCF.

4.2 Special Purpose Registers

4.2.1 A (Accumulator)

Internal data transfer, or instruction operand holding.

A non-addressable register.

4.2.2 CONT (Control Register)

/PHEN

/INT

PAB

PSR2

PSR1

PSR0

Bit 7 (/PHEN)

I/O pin pull-high enable flag.

0: For P60~P67, P74~P75 and P90~P95, the pull-high function is

enabled.

1: The pull-high function is disabled.

EM78P451WM Datasheet(PDF) 14 Page - ELAN Microelectronics Corp

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