LTC3370 datasheet(17/20 Pages) AD

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LTC3302

Rev. 0

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thermal vias. These layers spread heat dissipated by

the LTC3302.

4. Connect the ground side of any FB and EN compo-

nents to AGND (Pin 11). Connect a 1μF de-coupling

capacitor from AVIN (Pin 12) to AGND. Power the

AVIN pin by connecting a 10Ω filter resistor from the

VIN supply to AVIN.

Connect the AGND pin to the rest of the PCB ground

plane in only one location, to prevent transient cur-

rents in the ground plane from also flowing through the

AGND trace. Optionally, connect the AGND pin to the

negative terminal of the output capacitor at the load.

This reduces any load regulation caused by voltage

drops between the ground at the load and the LTC3302

voltage reference ground. The AGND node carries very

little current and can be a minimal size trace.

5. Care should be taken in the layout of the PCB to ensure

good heat sinking of the LTC3302. The heat generated

internal to the package is concentrated near the power

MOSFETs and mostly flows out of the VIN and PGND

pins to be spread on the PCB.

Connect the PGND pins (Pins 6, 7) to a large metal

area on the top layer. Connect the top layer ground

metal to ground plane(s) on lower levels with many

thermal vias. These layers spread heat dissipated by

the LTC3302. Also, connect the VIN pins (Pins 2, 3) to

a large metal plane with low thermal impedance.

The junction temperature, TJ, is calculated from the

ambient temperature, TA as given by Equation 10.

TJ = TA + (PD • θJA)

(10)

Where θJA is approximately 37.6°C/W to 48.9°C/W,

layout dependent.

Power dissipation within the LTC3302 is estimated by

calculating the total power loss from an efficiency mea-

surement and subtracting the inductor loss.

The LTC3302 evaluation kit PCB has a θJA that is

approximately 37.6°C/W, compared to approximately

48.9°C/W for a JEDEC 2S2P PCB. This is a 25% reduc-

tion in thermal impedance, and an example for how

much a good layout can improve thermal performance.

APPLICATIONS INFORMATION

Figure 3. Recommended PCB Layout

VOUT

CIN1

CIN2

AGND

VIN

GROUND PLANE ON LAYER 2

GND

(OPT)

RAVIN CAVIN

SENSE

TRACE

SW NODE

ON LAYER 2

3302 F03

COUT2

COUT1

4 5

11 10 9

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