47L64 datasheet(11/29 Pages) MICROCHIP

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Preliminary

DS20006168B-page 11

47L64

4.0

FUNCTIONAL DESCRIPTION

4.0.1

PRINCIPLES OF OPERATION

The 47L64 is a 64-Kbit serial EERAM designed to

support a bidirectional two-wire bus and data

transmission protocol (I2C). A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus has to be

controlled by a master device which generates the

Start and Stop conditions, while the 47L64 works as

slave. Both master and slave can operate as

transmitter or receiver but the master device

determines which mode is active.

4.1

BUS CHARACTERISTICS

4.1.1

SERIAL INTERFACE

The following

bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 4-1).

4.1.1.1

Bus Not Busy (A)

Both data and clock lines remain high.

4.1.1.2

Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All com-

mands must be preceded by a Start condition.

4.1.1.3

Stop Data Transfer (C)

A low-to-high transition of the SDA line while the clock

(SCL) is high determines a Stop condition. All opera-

tions must end with a Stop condition.

4.1.1.4

Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a Start condition and

terminated with a Stop condition. The number of the

data bytes transferred between the Start and Stop

conditions is determined by the master device.

4.1.1.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an Acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this Acknowledge

bit.

A device that acknowledges must pull down the SDA

line during the Acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of

the Acknowledge related clock pulse. Of course, setup

and hold times must be taken into account. During

reads, a master must signal an end of data to the slave

by NOT generating an Acknowledge bit on the last byte

that has been clocked out of the slave. In this case, the

slave (47L64) will leave the data line high to enable the

master to generate the Stop condition.

The 47L64 will generate an Acknowledge bit on

receiving a correct control byte and following address

and data bytes. Table 4-1 summarizes these situations.

The device will not generate Acknowledge bits for any

bytes following if the control byte is incorrect, such as

when the address bits do not match the A1, A2 pins,

see

Section 4.2 “Device Addressing”.

FIGURE 4-1:

DATA TRANSFER SEQUENCE ON THE SERIAL BUS

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

START

CONDITION

SCL

SDA

(A)

(B)

(D)

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