AD9879 datasheet(12/24 Pages) AD

12 / 24 page

REV. 0

–12–

AD9879

The formula for the combined output level calculation of the

AD9879 fine gain and AD8327 or AD8322 coarse gain is:

fine

coarse

8327

9877 0

() + () -

()

fine

coarse

8322

9877 0

() + () -

()

with:

fine = decimal value of Bits [3:0]

coarse = decimal value of Bits [7:8]

V9877(0): Level at AD9879 output in dBmV for fine = 0.

V8327: Level at output of AD8327 in dBmV.

V8322: Level at output of AD8322 in dBmV.

DEVICE OVERVIEW

To gain a general understanding of the AD9879, it is helpful to

refer to Figure 1, which displays a block diagram of the device

architecture. The device consists of a transmit path, receive path,

and auxiliary functions, such as a DPLL, a sigma-delta DAC,

a serial control port, and a cable amplifier interface.

Transmit Path

The transmit path contains an interpolation filter, a complete

quadrature digital upconverter, an inverse sinc filter, and a

TXIQ

TXSYNC

MCLK

REFCLK

CA_PORT

PROFILE

SPORT

RXIQ[3:0]

RXSYNC

IF[11:0]

FSADJ

XTAL

OSCIN

- _OUT

FLAG1

I INPUT

Q INPUT

IF10 INPUT

IF12 INPUT

VIDEO INPUT

AD9879

DATA

ASSEMBLER

QUADRATURE

MODULATOR

FIR LPF

CIC LPF

COS

SIN

(fIQCLK)

(fSYSCLK)

(fOSCIN)

(fMCLK)

DAC GAIN CONTROL

PLL

OSCIN

DDS

MUX

INTERFACE

PROFILE

SELECT

SERIAL

INTERFACE

SINC–1

MUX

DAC

CLAMP LEVEL

ADC

MUX

DAC

(fOSCIN)

RXPORT

- INPUT REG

–

—

SINC–1

BYPASS

Figure 1. Block Diagram

12-bit current output DAC. The maximum output current of the

DAC is set by an external resistor. The Tx output PGA provides

additional transmit signal level control.

The transmit path interpolation filter provides an upsampling

factor of 16 with an output signal bandwidth as high as 5.8 MHz.

Carrier frequencies up to 65 MHz with 26 bits of frequency

tuning resolution can be generated by the direct digital synthesizer

(DDS). The transmit DAC resolution is 12 bits and can run at

sampling rates as high as 232 MSPS.

Analog output scaling from 0 dB to 7.5 dB in 0.5 dB steps is

available to preserve SNR when reduced output levels are required.

Data Assembler

The AD9879 data path operates on two 12-bit words, the I and Q

components, that form a complex symbol. The data assembler

builds the 24-bit complex symbols from four consecutive 6-bit

nibbles read over the TxIQ[5:0] bus. The nibbles are strobed

synchronous to the master clock, MCLK, into the data assembler.

A high level on TxSYNC signals the start of a transmit symbol.

The first two nibbles of the symbol form the I component, the

second two nibbles form the Q component. Symbol components

are assumed to be in twos complement format. The timing of

the interface is fully described in the Transmit Timing section

of this data sheet.

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