AD9879 datasheet(13/24 Pages) AD

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AD9879

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INTERPOLATION FILTER

Once through the Data Assembler, the IQ data streams are fed

through a 4

FIR low-pass filter and a 4

Cascaded Integrator-

Comb (CIC) low-pass filter. The combination of these two filters

results in the sample rate increasing by a factor of 16. In addi-

tion to the sample rate increase, the half-band filters provide the

low-pass filtering characteristic necessary to suppress the spectral

images between the original sampling frequency and the new

(16

higher) sampling frequency.

DIGITAL UPCONVERTER

The digital quadrature modulator stage following the CIC filters

is used to frequency shift (upconvert) the baseband spectrum of

the incoming data stream up to the desired carrier frequency. The

carrier frequency is controlled numerically by a Direct Digital

Synthesizer (DDS). The DDS uses the internal system clock

(fSYSCLK) to generate the desired carrier frequency with a high

degree of precision. The carrier is applied to the I and Q multi-

pliers in quadrature fashion (90

∞ phase offset) and summed to

yield a data stream that is the modulated carrier. The modulated

carrier becomes the 12-bit sample sent to the DAC.

The receive path contains a 12-bit ADC, a 10-bit ADC, and a dual

7-bit ADC. All internally required clocks and an output system

clock are generated by the PLL from a single crystal or clock input.

The 12-bit and 10-bit IF ADCs can convert direct IF inputs up

to 70 MHz and run at sample rates up to 33 MSPS. A video

input with an adjustable signal clamping level along with the

10-bit ADC allow the AD9879 to process an NTSC and a

QAM channel simultaneously.

The programmable sigma-delta DAC can be used to control

external components, such as variable gain amplifiers (VGAs) or

voltage controlled tuners. The CAPORT provides an interface

to the AD8321/AD8323 or AD8322/AD8327 programmable

gain amplifier (PGA) cable drivers enabling host processor

control via the MxFE SPORT.

OSCIN Clock Multiplier

The AD9879 can accept either an input clock into the OSCIN

Pin or a fundamental mode XTAL across the OSCIN Pin and

XTAL Pins as the devices main clock source. The internal PLL

then generates the fSYSCLK signal from which all other internal

signals are derived.

The DAC uses fSYSCLK as its sampling clock. For DDS applications,

the carrier is typically limited to about 30% of fSYSCLK. For a

65 MHz carrier, the system clock required is above 216 MHz.

The OSCIN multiplier function maintains clock integrity as

evidenced by the AD9879’s systems excellent phase noise char-

acteristics and low clock-related spur in the output spectrum.

External loop filter components consisting of a series resistor

(1.3 k

W) and capacitor (0.01 mF) provide the compensation zero

for the OSCIN multiplier PLL loop. The overall loop perfor-

mance has been optimized for these component values.

DPLL-A CLOCK DISTRIBUTION

Figure 1 shows the clock signals used in the transmit path. The

DAC sampling clock, fDAC, is generated by DPLL-A. FDAC has

a frequency equal to the L

¥ fOSCIN, where fOSCIN is the internal

signal generated either by the crystal oscillator when a crystal is

connected between the OSCIN and XTAL pins, or by the clock

that is fed into the OSCIN pin, and L is the multiplier programmed

through the serial port. L can have the values of 1, 2, 3, or 8.

The transmit path expects a new half word of data at the rate of

fCLK-A. When the Tx multiplexer is enabled, the frequency of Tx

Port is:

CLK

DAC

OSCIN

=¥

=¥ ¥

where K is the interpolation factor.

The interpolation factor can be programmed to be 1, 2, or 4. When

the Tx multiplexer is disabled, the frequency of the Tx Port is:

CLK

DAC

OSCIN

== ¥

Receive Section

The AD9879 includes two high speed, high performance ADCs.

The 10-bit and 12-bit direct IF ADC’s deliver excellent

undersampling performance with input frequencies as high as

70 MHz. The sampling rate can be as high as 33 MSPS.

The ADC sampling frequency can be derived directly from the

OSCIN signal or from the on-chip OSCIN multiplier. For highest

dynamic performance, it is recommended to choose an OSCIN

frequency that can directly be used as the ADC sampling clock.

Digital IQ ADC outputs are multiplexed to one 4-bit bus, clocked

by a frequency (fMCLK) of four times the sampling rate. The IF

ADCs use a multiplexed 12-bit interface with an output word

rate of fMCLK.

CLOCK AND OSCILLATOR CIRCUITRY

The AD9879’s internal oscillator generates all sampling clocks

from a simple, low cost, parallel resonance, fundamental fre-

quency quartz crystal. Figure 2 shows how the quartz crystal is

connected between OSCIN (Pin 61) and XTAL (Pin 60) with

parallel resonant load capacitors as specified by the crystal

manufacturer. The internal oscillator circuitry can also be

overdriven by a TTL-level clock applied to OSCIN with XTAL

left unconnected.

OSCIN

MCLK

=¥

An internal phase-locked loop (PLL) generates the DAC sampling

frequency, fSYSCLK, by multiplying OSCIN frequency M times.

The MCLK signal (Pin 23), fMCLK, is derived by dividing

fSYSCLK by 4.

SYSCLK

OSCIN

=¥

MCLK

OSCIN

=¥

An external PLL loop filter (Pin 57) consisting of a series resistor

and ceramic capacitor (Figure 15, R1 = 1.3 k

W, C12 = 0.01 F) is

required for stability of the PLL. Also, a shield surrounding these

components is recommended to minimize external noise coupling

into the PLL’s voltage controlled oscillator input (guard trace

connected to AVDDPLL).

Figure 1 shows that ADCs are either sampled directly by a low

jitter clock at OSCIN or by a clock that is derived from the PLL

output. Operating modes can be selected in Register 8. Sampling

the ADCs directly with the OSCIN clock requires MCLK to be

programmed to be twice the OSCIN frequency.

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