AD9879 datasheet(19/24 Pages) AD

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REV. 0

AD9879

–19–

Tx Signal Level Considerations

The quadrature modulator itself introduces a maximum gain of

3 dB in signal level. To visualize this, assume that both the I data

and Q data are fixed at the maximum possible digital value, x.

Then the output of the modulator, z is:

zx cos

x sin

()

[]

ωω

–

Figure 14. 16-Quadrature Modulation

It can be shown that |z| assumes a maximum value of |z| =

2 + x2) =

√2 (a gain of +3 dB). However, if the same number

of bits were used to represent the |z|values, as is used to repre-

sent the x values, an overflow would occur. To prevent this

possibility, an effective –3 dB attenuation is internally imple-

mented on the I and Q data path:

() =









LOW-PASS

FILTER

AD832x

DAC

AD9879

VARIABLE GAIN

CABLE DRIVER

AMPLIFIER

CA_DATA

CA_CLK

CA_EN

Figure 15. 16-Quadrature Modulation

The following example assumes an PK/rms level of 10 dB:

Maximum Symbol Component Input Value

LSBs

±−

() =±

2047

0 2

2000

Maximum Complex Input RMS Value

LSBs

Pk rms dB

LSBs rms

±−

() =

2000

1265

The maximum complex input rms value calculation uses both

I and Q symbol components that add a factor of 2 (= 6 dB) to the

formula. Table VII shows typical I-Q input test signals with ampli-

tude levels related to 12-bit full scale (FS).

Tx Throughput and Latency

Data inputs effect the output fairly quickly but remain effective

due to AD9879’s filter characteristics. Data transmit latency

through the AD9879 is easiest to describe in terms of fSYSCLK

clock cycles (4 fMCLK). The numbers quoted are when an effect

is first seen after an input value change.

Latency of I/Q data entering the data assembler (AD9879 input)

to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK

cycles). DC values applied to the data assembler input will take

up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate

and settle at the DAC output.

Frequency hopping is accomplished via changing the PROFILE

input pin. The time required to switch from one frequency to

another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles).

D/A Converter

A 12-bit digital-to-analog converter (DAC) is used to convert

the digitally processed waveform into an analog signal. The

worst-case spurious signals due to the DAC are the harmonics

of the fundamental signal and their aliases (please see the

Analog Devices DDS Tutorial at: www.analog.com/dds). The

conversion process will produce aliased components of the fun-

damental signal at n

fSYSCLK

± f

CARRIER (n = 1, 2, 3). These

are typically filtered with an external RLC filter at the DAC

output. It is important for this analog filter to have a sufficiently

flat gain and linear phase response across the bandwidth of

interest so as to avoid modulation impairments. A relatively

inexpensive seventh order elliptical low-pass filter is sufficient to

suppress the aliased components for HFC network applications.

The AD9879 provides true and complement current outputs.

The full-scale output current is set by the RSET resistor at Pin 49

and the DAC Gain register. Assuming maximum DAC gain, the

value of RSET for a particular full-scale IOUT is determined using

the following equation:

SET

DACRSET

OUT

39 4

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.4/0.02)

Ω, or approximately 2 kΩ.

The following equation calculates the full-scale output current

including the programmable DAC gain control.

NGAIN

OUT

SET

=×

∧

[. /

]

((– .

) /

)

39 4

7 5

0 5

where NGAIN is the value of DAC Fine Gain Control[3:0].

Table VII. I–Q Input Test Signals

Analog Output

Digital Input

Input Level

Modulator Output Level

Single Tone (fC – f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 90 ) = –sin(f)

FS – 0.2 dB

Single Tone (fC + f)

I = cos(f)

FS – 0.2 dB

FS – 3.0 dB

Q = cos(f + 270 ) = +sin(f)

FS – 0.2 dB

Dual Tone (fC

I = cos(f)

FS – 0.2 dB

Q = cos(f + 180 ) = –cos(f) or Q = +cos(f)

FS – 0.2 dB

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