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AD9879

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Serial Interface Port Pin Description

SCLK—Serial Clock. The serial clock pin is used to synchronize

data transfers from the AD9879 and to run the serial port state

machine. The maximum SCLK frequency is 15 MHz. Input

data to the AD9879 is sampled on the rising edge of SCLK.

Output data changes on the falling edge of SCLK.

CS—Chip Select. Active low input starts and gates a communi-

cation cycle. It allows multiple devices to share a common serial

port bus. The SDO and SDIO pins go to a high impedance

state when

CS is high. Chip select should stay low during the

entire communication cycle.

SDIO—Serial Data I/O. Data is always written into the AD9879

on this pin. However, this pin can be used as a bidirectional

data line. The configuration of this pin is controlled by Bit 7 of

pin as unidirectional.

SDO—Serial Data Out. Data is read from this pin for protocols

that use separate lines for transmitting and receiving data. In the

case where the AD9879 operates in a single bidirectional I/O

mode, this pin does not output data and is set to a high imped-

ance state.

MSB/LSB Transfers

The AD9879 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by the LSB First Bit in Register 0.

The default is MSB first.

When this bit is set active high, the AD9879 serial port is in

LSB first format. In LSB first mode, the instruction byte and

data bytes must be written from the least significant bit to the

most significant bit. In LSB first mode, the serial port internal

byte address generator increments for each byte of the multibyte

communication cycle.

When this bit is set default low, the AD9879 serial port is in

MSB first format. In MSB first mode, the instruction byte and

data bytes must be written from the most significant bit to the

least significant bit. In MSB first mode, the serial port internal byte

address generator decrements for each byte of the multibyte

communication cycle.

When incrementing from 0x1F, the address generator changes

to 0x00. When decrementing from 0x00, the address generator

changes to 0x1F.

Notes on Serial Port Operation

The AD9879 serial port configuration bits reside in Bits 6 and 7

of Register Address 00h. It is important to note that the con-

figuration changes immediately upon writing to the last bit of

the register. For multibyte transfers, writing to this register may

occur during the middle of the communication cycle. Care must

be taken to compensate for this new configuration for the

remaining bytes of the current communication cycle.

The same considerations apply to setting the reset bit in Register

Address 00h. All other registers are set to their default values, but

the software reset does not affect the bits in Register Address 00h.

It is recommended to use only single byte transfers when chang-

ing serial port configurations or initiating a software reset.

A write to Bits 1, 2, and 3 of Address 00h with the same logic

levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows

the user to reprogram a lost serial port configuration and to

reset the registers to their default values. A second write to

Address 00h with the RESET bit low and the serial port

configuration as specified above (XY) reprograms the OSCIN

multiplier setting. A changed fSYSCLK frequency is stable after a

maximum of tbd fMCLK cycles (wake-up time).

SCLK

SDIO

SDO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

R/W

D7n D6n

D20 D10 D00

D7n D6n

D20 D10 D00

Figure 8a. Serial Register Interface Timing MSB First

SCLK

SDIO

SDO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

N1 R/W

D6n D7n

D00 D10 D20

D6n D7n

D00 D10 D20

Figure 8b. Serial Register Interface Timing LSB First

SCLK

SDIO

INSTRUCTION BIT 7

INSTRUCTION BIT 6

tSCLK

tDS

tPWL

tPWH

tDS

tDH

Figure 9. Timing Diagram for Register Write to AD9879

SCLK

SDIO

DATA BIT N

tDV

DATA BIT N

SDO

Figure 10. Timing Diagram for Register Read

TRANSMIT PATH (Tx)

Transmit Timing

The AD9879 provides a master clock MCLK and expects 6-bit

multiplexed TxIQ data on each rising edge. Transmit symbols

are framed with the TxSYNC input. TxSYNC high indicates

the start of a transmit symbol. Four consecutive 6-bit data pack-

ages form a symbol (I MSB, I LSB, Q MSB, and Q LSB).

Data Assembler

The input data stream is representative complex data. Two 6-bit

words form a 12-bit symbol component (in twos complement

format). Four input samples are required to produce one I/Q

data pair. The I/Q sample rate fIQCLK at the input to the first

half-band filter is a quarter of the input data rate fMCLK. The I/Q

sample rate fIQCLK puts a bandwidth limit on the maximum

transmit spectrum. This is the familiar Nyquist limit and is

equal to one-half fIQCLK that hereafter will be referred to as fNYQ.

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